diff options
Diffstat (limited to 'target/linux/bcm53xx/patches-5.4/043-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch')
| -rw-r--r-- | target/linux/bcm53xx/patches-5.4/043-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch | 203 |
1 files changed, 203 insertions, 0 deletions
diff --git a/target/linux/bcm53xx/patches-5.4/043-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch b/target/linux/bcm53xx/patches-5.4/043-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch new file mode 100644 index 0000000000..ef29266d0b --- /dev/null +++ b/target/linux/bcm53xx/patches-5.4/043-v6.5-0005-ARM-dts-BCM5301X-Relicense-AXI-interrupts-code-to-th.patch @@ -0,0 +1,203 @@ +From 3b3e35b279bee5e51580c648399e20323467f58c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl> +Date: Mon, 15 May 2023 17:19:21 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: Relicense AXI interrupts code to the GPL + 2.0+ / MIT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Those entries were added by: +1. Hauke in commits dec378827c4a ("ARM: BCM5301X: Add IRQs to Broadcom's + bus-axi in DTS file") and 1f80de6863ca ("ARM: BCM5301X: add IRQ + numbers for PCIe controller") +2. Florian in the commit 2cd0c0202f13 ("ARM: dts: BCM5301X: Add SRAB + interrupts") + +Move them to the bcm-ns.dtsi which uses dual licensing. That syncs more +Northstar code to be based on the same licensing schema. + +Signed-off-by: Rafał Miłecki <rafal@milecki.pl> +Cc: Hauke Mehrtens <hauke@hauke-m.de> +Cc: Florian Fainelli <f.fainelli@gmail.com> +Acked-by: Hauke Mehrtens <hauke@hauke-m.de> +Link: https://lore.kernel.org/r/20230515151921.25021-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> +--- + arch/arm/boot/dts/bcm-ns.dtsi | 73 ++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm5301x.dtsi | 75 --------------------------------- + 2 files changed, 73 insertions(+), 75 deletions(-) + +--- a/arch/arm/boot/dts/bcm-ns.dtsi ++++ b/arch/arm/boot/dts/bcm-ns.dtsi +@@ -92,6 +92,79 @@ + #address-cells = <1>; + #size-cells = <1>; + ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0x000fffff 0xffff>; ++ interrupt-map = ++ /* ChipCommon */ ++ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Switch Register Access Block */ ++ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* PCIe Controller 0 */ ++ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* PCIe Controller 1 */ ++ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* PCIe Controller 2 */ ++ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* USB 2.0 Controller */ ++ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* USB 3.0 Controller */ ++ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 0 */ ++ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 1 */ ++ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 2 */ ++ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 3 */ ++ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* NAND Controller */ ++ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; ++ + chipcommon: chipcommon@0 { + reg = <0x00000000 0x1000>; + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -3,8 +3,6 @@ + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs + * +- * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> +- * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +@@ -72,79 +70,6 @@ + }; + + axi@18000000 { +- #interrupt-cells = <1>; +- interrupt-map-mask = <0x000fffff 0xffff>; +- interrupt-map = +- /* ChipCommon */ +- <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Switch Register Access Block */ +- <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, +- <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 0 */ +- <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, +- <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 1 */ +- <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, +- <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, +- +- /* PCIe Controller 2 */ +- <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, +- <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, +- +- /* USB 2.0 Controller */ +- <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, +- +- /* USB 3.0 Controller */ +- <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 0 */ +- <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 1 */ +- <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 2 */ +- <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, +- +- /* Ethernet Controller 3 */ +- <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, +- +- /* NAND Controller */ +- <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, +- <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; +- + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; |