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* ipq40xx: Add reserved memory for WPJ428Sven Eckelmann2018-03-231-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The APPSBL and anything after that it not allowed to touch some of the memory regions which are used by other components. Still trying to write to the memory can lead to sudden device restarts (IPQ40xx) # mw 87e80000 0 data abort pc : [<873149f8>] lr : [<87308578>] sp : 86edfc28 ip : 86ef4412 fp : 00000000 r10: 00000000 r9 : 00000000 r8 : 86edff68 r7 : 00000003 r6 : 8737e624 r5 : 86ef4420 r4 : 8736c154 r3 : 00000000 r2 : 00000010 r1 : 00000000 r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... The device manufacturer only provided a very rough list of regions: * rsvd1: 0x87000000 0x500000 * wifi_dump: 0x87500000 0x600000 * rsvd2: 0x87b00000 0x500000 A more detailed list for devices using the AP.DK reference design memory maps was provided by Roman Yeryomin <roman@advem.lv> in commit 56f2df879fd ("ipq806x: ipq4019: add ap-dk01.1-c1 board support"): * apps_bl: 0x87000000 0x400000 * sbl: 0x87400000 0x100000 * cnss_debug: 0x87500000 0x600000 * cpu_context_dump: 0x87b00000 0x080000 * tz_apps: 0x87b80000 0x280000 * smem: 0x87e00000 0x080000 * tz: 0x87e80000 0x180000 The u-boot function ipq_fdt_mem_rsvd_fixup seems to suggest that only the rsvd2 (tz_apps, smem, tz) should be protected. All other regions would have been removed by it when CONFIG_QCA_APPSBL_DLOAD is not enabled. This allows to reduce the 16MB reserved memory region to only 4.5MB. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
* ipq40xx: Use detailed reserved memory for A42Sven Eckelmann2018-03-231-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The APPSBL and anything after that it not allowed to touch some of the memory regions which are used by other components. Still trying to write to the memory can lead to sudden device restarts (IPQ40xx) # mw 87e80000 0 data abort pc : [<873149f8>] lr : [<87308578>] sp : 86edfc28 ip : 86ef4412 fp : 00000000 r10: 00000000 r9 : 00000000 r8 : 86edff68 r7 : 00000003 r6 : 8737e624 r5 : 86ef4420 r4 : 8736c154 r3 : 00000000 r2 : 00000010 r1 : 00000000 r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... The device manufacturer only provided a very rough list of regions: * rsvd1: 0x87000000 0x500000 * wifi_dump: 0x87500000 0x600000 * rsvd2: 0x87b00000 0x500000 A more detailed list for devices using the AP.DK reference design memory maps was provided by Roman Yeryomin <roman@advem.lv> in commit 56f2df879fd ("ipq806x: ipq4019: add ap-dk01.1-c1 board support"): * apps_bl: 0x87000000 0x400000 * sbl: 0x87400000 0x100000 * cnss_debug: 0x87500000 0x600000 * cpu_context_dump: 0x87b00000 0x080000 * tz_apps: 0x87b80000 0x280000 * smem: 0x87e00000 0x080000 * tz: 0x87e80000 0x180000 The u-boot function ipq_fdt_mem_rsvd_fixup seems to suggest that only the rsvd2 (tz_apps, smem, tz) should be protected. All other regions would have been removed by it when CONFIG_QCA_APPSBL_DLOAD is not enabled. This allows to reduce the 16MB reserved memory region to only 4.5MB. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
* ipq40xx: Remove phy reset gpio from Cisco Meraki MR33Sven Eckelmann2018-03-231-1/+0
| | | | | | | | There is currently no code to read the phy reset gpios for the ethernet PHY. It would also have been better to use the more common name "phy-reset-gpios" for this property. Signed-off-by: Sven Eckelmann <sven@narfation.org>
* ipq40xx: Adjust SoC name of AVM Fritz!Box 4040Sven Eckelmann2018-03-233-2/+2
| | | | | | | The AVM Fritz!Box 4040 uses an IPQ4018 as SoC and not an IPQ4019. The DTS must be adjusted to reflect this. Signed-off-by: Sven Eckelmann <sven@narfation.org>
* ipq40xx: Use constant to set gpio active low/highSven Eckelmann2018-03-237-8/+9
| | | | | | | | | The GPIO configuration in the DTS have as third parameter the active low/high configuration. This parameter is not easy to parse by humans when it is only set to 0/1. It is better to use the predefined constants GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
* ipq40xx: Fix DTS status parameter valuesSven Eckelmann2018-03-234-47/+47
| | | | | | | | The "Devicetree Speciļ¬cation, Release v0.2 - 2.3.4 status" [1] only allows the "okay" value for an operational device. The "ok" value will be accepted by the kernel but should be avoided. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
* ipq40xx: Provide prefered DTS config name for A42Sven Eckelmann2018-03-231-0/+1
| | | | | | | | The OpenMesh A42 will use the default config entry in the FIT when no other on is found but prefers the config@om.a42. This only becomes relevant when a Multi-FIT image is prepared for this device. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
* ipq40xx: Remove SUPPORTED_DEVICES for A42Sven Eckelmann2018-03-231-1/+0
| | | | | | | The SUPPORTED_DEVICES will be defined automatically via Device/Default in ipq40xx. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
* ipq40xx: fix GL.iNet GL-B1300Mathias Kresin2018-03-172-319/+0
| | | | | | | | | | | The deletion of the mdio node childs was meant for testing and were committed accidentally. Without the mdio nodes the network isn't initialised. While at it, remove the orphaned qcom-ipq4019-gl-b1300.dts as well. Fixes: FS#1439 Signed-off-by: Mathias Kresin <dev@kresin.me>
* ipq40xx: add support for Compex WPJ428Sven Eckelmann2018-03-176-1/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * QCA IPQ4028 * 256 MB of RAM * 32 MB of SPI NOR flash (mx25l25635e) * 128 MB of SPI NAND flash (gd5f1gq4ucy1g) * 2T2R 2.4 GHz - QCA4019 hw1.0 (SoC) - uses AP-DK03 BDF from QCA4019/hw1.0/board-2.bin * 2T2R 5 GHz - QCA4019 hw1.0 (SoC) - uses AP-DK03 BDF from QCA4019/hw1.0/board-2.bin * 2 fully software controllable GPIO-LEDs * 2 additional GPIO-LEDs which also affect the SIM card detection * 1x button (reset) * 1x GPIO buzzer * 1x USB (xHCI) * 1x NGFF (USB-only with Dual-SIM support, untested) * TTL pins are on board (R124 is next to GND, then follows: RX, TX, VCC) * 2x gigabit ethernet - phy@mdio4: + Manual: Ethernet port 0 + gmac0 (ethaddr) in original firmware + 802.3af POE (HV version) + 24v passive POE (LV version) - phy@mdio3: + Manual: Ethernet port 1 + gmac1 (eth1addr) in original firmware * DC Jack connector + 24-56V (HV version) + 12-24V (LV version) The SPI NAND flash isn't supported at the moment. The bootloader has to be updated before OpenWrt is installed to fix a reboot problem. The nor-ipq40xx-single.img from https://downloads.compex.com.sg/?dir=uploads/QSDK/QCA-Reference/WPJ428/b170123-IPQ40xx-Reference-Firmware has to be downloaded and the transfered in u-boot via TFTP set ipaddr 192.168.1.11 set serverip 192.168.1.10 ping ${serverip} tftpboot 0x84000000 nor-ipq40xx-single.img imgaddr=0x84000000 && source $imgaddr:script The sysupgrade image can be installed directly on flash using u-boot: sf probe tftpboot 0x84000000 openwrt-ipq40xx-compex_wpj428-squashfs-sysupgrade.bin sf erase 0x00180000 +$filesize sf write 0x84000000 0x00180000 $filesize bootipq The initramfs image can be started using tftpboot 0x82000000 openwrt-ipq40xx-compex_wpj428-initramfs-fit-uImage.itb set fdt_high 0x83000000 bootm 0x82000000 The used SIM card slot can be changed using # slot 1 (also enables orange LED) echo 1 > /sys/class/gpio/gpio3/value # slot 2 echo 0 > /sys/class/gpio/gpio3/value It can be checked whether a SIM card is inserted in the current slot and the red LED is subsequently on via: echo 2 > /sys/class/gpio/export cat /sys/class/gpio/gpio2/value Signed-off-by: Sven Eckelmann <sven@narfation.org>
* ipq40xx: add Cisco Meraki MR33 SupportChris Blake2018-03-1410-1/+861
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Cisco Meraki MR33 hardware highlights: SOC: IPQ4029 Quad-Core ARMv7 Processor rev 5 (v7l) Cortex-A7 DRAM: 256 MiB DDR3L-1600 @ 627 MHz Micron MT41K128M16JT-125IT NAND: 128 MiB SLC NAND Spansion S34ML01G200TFV00 (106 MiB usable) ETH: Qualcomm Atheros AR8035 Gigabit PHY (1 x LAN/WAN) + PoE WLAN1: QCA9887 (168c:0050) PCIe 1x1:1 802.11abgn ac Dualband VHT80 WLAN2: Qualcomm Atheros QCA4029 2.4GHz 802.11bgn 2:2x2 WLAN3: Qualcomm Atheros QCA4029 5GHz 802.11a/n/ac 2:2x2 VHT80 LEDS: 1 x Programmable RGB+White Status LED (driven by Ti LP5562 on i2c-1) 1 x Orange LED Fault Indicator (shared with LP5562) 2 x LAN Activity / Speed LEDs (On the RJ45 Port) BUTTON: one Reset button MISC: Bluetooth LE Ti cc2650 PG2.3 4x4mm - BL_CONFIG at 0x0001FFD8 AT24C64 8KiB EEPROM Kensington Lock Serial: WARNING: The serial port needs a TTL/RS-232 3V3 level converter! The Serial setting is 115200-8-N-1. The board has a populated 1x4 0.1" header with half-height/low profile pins. The pinout is: VCC (little white arrow), RX, TX, GND. Flashing needs a serial adaptor, as well as patched ubootwrite utility (needs Little-Endian support). And a modified u-boot (enabled Ethernet). Meraki's original u-boot source can be found in: <https://github.com/riptidewave93/meraki-uboot/tree/mr33-20170427> Add images to do an installation via bootloader: 0. open up the MR33 and connect the serial console. 1. start the 2nd stage bootloader transfer from client pc: # ubootwrite.py --write=mr33-uboot.bin (The ubootwrite tool will interrupt the boot-process and hence it needs to listen for cues. If the connection is bad (due to the low-profile pins), the tool can fail multiple times and in weird ways. If you are not sure, just use a terminal program and see what the device is doing there. 2. power on the MR33 (with ethernet + serial cables attached) Warning: Make sure you do this in a private LAN that has no connection to the internet. - let it upload the u-boot this can take 250-300 seconds - 3. use a tftp client (in binary mode!) on your PC to upload the sysupgrade.bin (the u-boot is listening on 192.168.1.1) # tftp 192.168.1.1 binary put openwrt-ipq40xx-meraki_mr33-squashfs-sysupgrade.bin 4. wait for it to reboot 5. connect to your MR33 via ssh on 192.168.1.1 For more detailed instructions, please take a look at the: "Flashing Instructions for the MR33" PDF. This can be found on the wiki: <https://openwrt.org/toh/meraki/mr33> (A link to the mr33-uboot.bin + the modified ubootwrite is also there) Thanks to Jerome C. for sending an MR33 to Chris. Signed-off-by: Chris Blake <chrisrblake93@gmail.com> Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ipq40xx: add support for ASUS RT-AC58U/RT-ACRH13Christian Lamparter2018-03-1410-2/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for ASUS RT-AC58U/RT-ACRH13. hardware highlights: SOC: IPQ4018 / QCA Dakota CPU: Quad-Core ARMv7 Processor rev 5 (v7l) Cortex-A7 DRAM: 128 MiB DDR3L-1066 @ 537 MHz (1074?) NT5CC64M16GP-DI NOR: 2 MiB Macronix MX25L1606E (for boot, QSEE) NAND: 128 MiB Winbond W25NO1GVZE1G (cal + kernel + root, UBI) ETH: Qualcomm Atheros QCA8075 Gigabit Switch (4 x LAN, 1 x WAN) USB: 1 x 3.0 (via Synopsys DesignWare DWC3 controller in the SoC) WLAN1: Qualcomm Atheros QCA4018 2.4GHz 802.11bgn 2:2x2 WLAN2: Qualcomm Atheros QCA4018 5GHz 802.11a/n/ac 2:2x2 INPUT: one Reset and one WPS button LEDS: Status, WAN, WIFI1/2, USB and LAN (one blue LED for each) Serial: WARNING: The serial port needs a TTL/RS-232 3V3 level converter! The Serial setting is 115200-8-N-1. The board has an unpopulated 1x4 0.1" header. The pinout (VDD, RX, GND, TX) is printed on the PCB right next to the connector. U-Boot Note: The ethernet driver isn't always reliable and can sometime time out... Don't worry, just retry. Access via the serial console is required. As well as a working TFTP-server setup and the initramfs image. (If not provided, it has to be built from the OpenWrt source. Make sure to enable LZMA as the compression for the INITRAMFS!) To install the image permanently, you have to do the following steps in the listed order. 1. Open up the router. There are four phillips screws hiding behind the four plastic feets on the underside. 2. Connect the serial cable (See notes above) 3. Connect your router via one of the four LAN-ports (yellow) to a PC which can set the IP-Address and ssh and scp from. If possible set your PC's IPv4 Address to 192.168.1.70 (As this is the IP-Address the Router's bootloader expects for the tftp server) 4. power up the router and enter the u-boot choose option 1 to upload the initramfs image. And follow through the ipv4 setup. Wait for your router's status LED to stop blinking rapidly and glow just blue. (The LAN LED should also be glowing blue). 3. Connect to the OpenWrt running in RAM The default IPv4-Address of your router will be 192.168.1.1. 1. Copy over the openwrt-sysupgrade.bin image to your router's temporary directory # scp openwrt-sysupgrade.bin root@192.168.1.1:/tmp 2. ssh from your PC into your router as root. # ssh root@192.168.1.1 The default OpenWrt-Image won't ask for a password. Simply hit the Enter-Key. Once connected...: run the following commands on your temporary installation 3. delete the "jffs2" ubi partition to make room for your new root partition # ubirmvol /dev/ubi0 --name=jffs2 4. install OpenWrt on the NAND Flash. # sysupgrade -v /tmp/openwrt-sysupgrade.bin - This will will automatically reboot the router - Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ipq40xx: fix GL.iNet GL-B1300 supportMathias Kresin2018-03-144-6/+322
| | | | | | | | | | | | | | | | | | | | Rename the dts file to match the used SoC type and drop the unnecessary KERNEL_INSTALL from the image build code. Remove the fixed rootfs and kernel partitions and create an image with rootfs appended after kernel. Setup a switch portmap matching the hardware and a default network/switch configuration to make make the second lan port working. Use eth0 as lan to have it consistent accross the target. Use the power LED to indicate the boot status. Sort the SoC entries within the dts by address and use dtc labels whenever possible. Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
* ipq40xx: remove block- and pagesize from FB4040David Bauer2018-03-142-24/+0
| | | | | | | | | | | | This removes the block- and pagesize from the FritzBox 4040 image description, fixing incorrectly working sysupgrade. With this commit, the default values for block- and pagesize are used. Signed-off-by: David Bauer <mail@david-bauer.net> [chunkeey@gmail.com: removed 105-mtd-nor-add-mx25l25635f.patch as well] Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ipq40xx: OpenMesh A42 overhaulChristian Lamparter2018-03-143-88/+81
| | | | | | | | | | | Sort the soc entries in the dts by address and use dtc labels whenever possible. Adjust the DTS files, the OpenMesh A42 is actually an IPQ4018 and not an IPQ4019. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ipq40xx: fix apss cpu overclocking spamChristian Lamparter2018-03-142-2/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's an interaction issue between the clk changes:" clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks " and the cpufreq-dt. cpufreq-dt is now spamming the kernel-log with the following: [ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP for freq 761142857 (-34) This only happens on certain devices like the Compex WPJ428 and AVM FritzBox!4040. However, other devices like the Asus RT-AC58U and Meraki MR33 work just fine. The issue stem from the fact that all higher CPU-Clocks are achieved by switching the clock-parent to the P_DDRPLLAPSS (ddrpllapss). Which is set by Qualcomm's proprietary bootcode as part of the DDR calibration. For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked at round 533 MHz (ddrpllsdcc = 190285714 Hz). whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz). Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ipq40xx/ipq806x: move qcom-dwc3 usb driver to genericMathias Kresin2018-03-141-33/+0
| | | | | | | If the a kernel package exists within multiple targets an error/warning is shown. Signed-off-by: Mathias Kresin <dev@kresin.me>
* ipq40xx: add targetJohn Crispin2018-03-1451-0/+25706
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: John Crispin <john@phrozen.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 13:52:58 +0000