From ca5c695a4522091234026e22e8336f05d65602ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Mon, 22 Aug 2022 14:02:36 +0200 Subject: kernel: bump 5.15 to 5.15.62 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deleted following upstreamed patches: bcm27xx: 950-0006-drm-vc4-hdmi-Fix-HPD-GPIO-detection.patch bcm27xx: 950-0420-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx: 950-0425-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx: 950-0432-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx: 950-0433-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx: 950-0435-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx: 950-0436-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx: 950-0437-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx: 950-0438-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx: 950-0443-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx: 950-0445-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch bcm27xx: 950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch bcm27xx: 950-0476-drm-vc4-Release-workaround-buffer-and-DMA-in-error-p.patch bcm27xx: 950-0477-drm-vc4-Correct-DSI-divider-calculations.patch bcm27xx: 950-0664-drm-vc4-dsi-Correct-max-divider-to-255-not-7.patch bcm53xx: 072-next-ARM_dts_BCM53015-add-mr26.patch mediatek: 920-linux-next-dts-mt7622-bpi-r64-fix-wps-button.patch Manually rebased following patches: bcm27xx: 950-0004-drm-vc4-hdmi-Remove-the-DDC-probing-for-status-detec.patch bcm27xx: 950-0700-net-phy-lan87xx-Decrease-phy-polling-rate.patch bcm27xx: 950-0711-drm-vc4-Rename-bridge-to-out_bridge.patch bcm27xx: 950-0713-drm-vc4-Remove-splitting-the-bridge-chain-from-the-d.patch bcm27xx: 950-0715-drm-vc4-Convert-vc4_dsi-to-using-a-bridge-instead-of.patch bcm27xx: 950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch bcm27xx: 950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch Runtime tested on turris-omnia and glinet-b1300. Tested-by: John Audia [bcm2711/RPi4B, mt7622/RT3200] Signed-off-by: Petr Štetiar --- ...-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch | 69 ---------------------- 1 file changed, 69 deletions(-) delete mode 100644 target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch (limited to 'target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch') diff --git a/target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch b/target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch deleted file mode 100644 index 9032f11794..0000000000 --- a/target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 671b5b9af51bd5296d4fe76155b3ba75c99000b9 Mon Sep 17 00:00:00 2001 -From: Dave Stevenson -Date: Mon, 13 Sep 2021 17:30:18 +0100 -Subject: [PATCH] drm/vc4: Reset HDMI MISC_CONTROL register. - -The HDMI block can repeat pixels for double clocked modes, -and the firmware is now configuring the block to do this as -the PV is doing it incorrectly when at 2pixels/clock. -If the kernel doesn't reset it then we end up with strange -modes. - -Reset MISC_CONTROL. - -Signed-off-by: Dave Stevenson ---- - drivers/gpu/drm/vc4/vc4_hdmi.c | 8 ++++++++ - drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 3 +++ - 2 files changed, 11 insertions(+) - ---- a/drivers/gpu/drm/vc4/vc4_hdmi.c -+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c -@@ -79,6 +79,9 @@ - #define VC5_HDMI_VERTB_VSPO_SHIFT 16 - #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) - -+#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 -+#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) -+ - #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) - - #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 -@@ -963,6 +966,11 @@ static void vc5_hdmi_set_timings(struct - reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; - HDMI_WRITE(HDMI_GCP_CONFIG, reg); - -+ reg = HDMI_READ(HDMI_MISC_CONTROL); -+ reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; -+ reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP); -+ HDMI_WRITE(HDMI_MISC_CONTROL, reg); -+ - HDMI_WRITE(HDMI_CLOCK_STOP, 0); - - spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); ---- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h -+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h -@@ -125,6 +125,7 @@ enum vc4_hdmi_field { - HDMI_VERTB0, - HDMI_VERTB1, - HDMI_VID_CTL, -+ HDMI_MISC_CONTROL, - }; - - struct vc4_hdmi_register { -@@ -235,6 +236,7 @@ static const struct vc4_hdmi_register __ - VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), - VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), - VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), -+ VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100), - VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), - VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), - VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), -@@ -315,6 +317,7 @@ static const struct vc4_hdmi_register __ - VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), - VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), - VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), -+ VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100), - VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), - VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), - VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), -- cgit v1.2.3