// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; #include #include #include #include "mt7981.dtsi" / { model = "Cetron CT3003"; compatible = "cetron,ct3003", "mediatek,mt7981"; aliases { serial0 = &uart0; label-mac-device = &gmac0; led-boot = &led_status_red; led-failsafe = &led_status_red; led-running = &led_status_green; led-upgrade = &led_status_green; }; chosen { stdout-path = "serial0:115200n8"; }; memory { reg = <0 0x40000000 0 0x10000000>; }; gpio-keys { compatible = "gpio-keys"; reset { label = "reset"; linux,code = ; gpios = <&pio 1 GPIO_ACTIVE_LOW>; }; wps { label = "wps"; linux,code = ; gpios = <&pio 0 GPIO_ACTIVE_HIGH>; }; }; leds { compatible = "gpio-leds"; led_status_red: led_status_red { function = LED_FUNCTION_STATUS; color = ; gpios = <&pio 3 GPIO_ACTIVE_LOW>; }; led_status_green: led_status_green { function = LED_FUNCTION_STATUS; color = ; gpios = <&pio 7 GPIO_ACTIVE_LOW>; }; }; }; ð { status = "okay"; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "2500base-x"; nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; fixed-link { speed = <2500>; full-duplex; pause; }; }; }; &mdio_bus { switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&pio>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; }; }; &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_flash_pins>; status = "okay"; spi_nand@0 { compatible = "spi-nand"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-max-frequency = <52000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; mediatek,nmbm; mediatek,bmt-max-ratio = <1>; mediatek,bmt-max-reserved-blocks = <64>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "BL2"; reg = <0x0000000 0x0100000>; read-only; }; partition@100000 { label = "u-boot-env"; reg = <0x0100000 0x0080000>; }; partition@180000 { label = "art"; reg = <0x0180000 0x0100000>; read-only; nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; #size-cells = <1>; macaddr_art_0: macaddr@0 { compatible = "mac-base"; reg = <0x0 0x6>; #nvmem-cell-cells = <1>; }; }; }; factory: partition@280000 { label = "Factory"; reg = <0x0280000 0x0100000>; read-only; }; partition@380000 { label = "FIP"; reg = <0x0380000 0x0200000>; read-only; }; partition@580000 { label = "ubi"; reg = <0x0580000 0x2000000>; }; partition@2580000 { label = "ubi_backup"; reg = <0x2580000 0x2000000>; }; partition@4580000 { label = "Config_backup"; reg = <0x4580000 0x0400000>; }; }; }; }; &switch { ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "wan"; nvmem-cells = <&macaddr_art_0 3>; nvmem-cell-names = "mac-address"; }; port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "2500base-x"; fixed-link { speed = <2500>; full-duplex; pause; }; }; }; }; &pio { spi0_flash_pins: spi0-pins { mux { function = "spi"; groups = "spi0", "spi0_wp_hold"; }; conf-pu { pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; drive-strength = ; bias-pull-up = ; }; conf-pd { pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; drive-strength = ; bias-pull-down = ; }; }; }; &uart0 { status = "okay"; }; &watchdog { status = "okay"; }; &wifi { status = "okay"; mediatek,mtd-eeprom = <&factory 0x0>; };