From 0c5b5243ad55ae744e790ba90c5ad37a93bd1377 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 11 Oct 2022 23:38:45 +0200 Subject: [PATCH] clk: qcom: ipq6018: workaround networking clock parenting Currently, networking clocks are only looked up by fw_name however, these are registered and setup by SSDK and are not available to the GCC driver at all, so work around that by providing a global name fallback. While we are here, provide global fallback for bias_pll_cc_clk and bias_pll_nss_noc_clk as well as these are fixed clocks also not available to the driver. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq6018.c | 39 +++++++++++++++++----------------- 1 file changed, 19 insertions(+), 20 deletions(-) --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -361,7 +361,7 @@ static const struct freq_tbl ftbl_nss_pp static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = { { .fw_name = "xo" }, - { .fw_name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll4.clkr.hw }, { .hw = &nss_crypto_pll.clkr.hw }, @@ -527,12 +527,12 @@ static const struct freq_tbl ftbl_nss_po static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = { { .fw_name = "xo" }, - { .fw_name = "uniphy0_gcc_rx_clk" }, - { .fw_name = "uniphy0_gcc_tx_clk" }, - { .fw_name = "uniphy1_gcc_rx_clk" }, - { .fw_name = "uniphy1_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" }, + { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map @@ -574,12 +574,12 @@ static const struct freq_tbl ftbl_nss_po static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = { { .fw_name = "xo" }, - { .fw_name = "uniphy0_gcc_tx_clk" }, - { .fw_name = "uniphy0_gcc_rx_clk" }, - { .fw_name = "uniphy1_gcc_tx_clk" }, - { .fw_name = "uniphy1_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" }, + { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map @@ -715,10 +715,10 @@ static const struct freq_tbl ftbl_nss_po static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = { { .fw_name = "xo" }, - { .fw_name = "uniphy0_gcc_rx_clk" }, - { .fw_name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = { @@ -751,10 +751,10 @@ static const struct freq_tbl ftbl_nss_po static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = { { .fw_name = "xo" }, - { .fw_name = "uniphy0_gcc_tx_clk" }, - { .fw_name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = { @@ -1898,12 +1898,11 @@ static const struct freq_tbl ftbl_ubi32_ { } }; -static const struct clk_parent_data - gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = { +static const struct clk_parent_data gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = { { .fw_name = "xo" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll2.clkr.hw }, - { .fw_name = "bias_pll_nss_noc_clk" }, + { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" }, }; static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {