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| author | Duncan Laurie <dlaurie@chromium.org> | 2016-10-28 09:07:49 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-10-28 18:59:46 +0200 |
| commit | c806e4cc59208afb8b00da0a2cd34909e6bb9fb3 (patch) | |
| tree | 417425ad4b9b2269da0032804ed2d7b00c903bf7 /3rdparty/chromeec | |
| parent | ffddf7beb455759e3d3962475deca52b88b19d5a (diff) | |
| download | coreboot-c806e4cc59208afb8b00da0a2cd34909e6bb9fb3.tar.gz coreboot-c806e4cc59208afb8b00da0a2cd34909e6bb9fb3.tar.bz2 coreboot-c806e4cc59208afb8b00da0a2cd34909e6bb9fb3.zip | |
skylake: Add GPIO macro for configuring inverted APIC input
Add a GPIO macro that allows a pin to be routed to the APIC with
the input inverted. This allows a normal interrupt to get used as
a GPE during firmware and still be used as a perhiperal interrupt
in the kernel.
BUG=chrome-os-partner:58666
TEST=boot en eve and use TPM IRQ in firmware and OS
Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17176
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to '3rdparty/chromeec')
0 files changed, 0 insertions, 0 deletions