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| author | Wolfgang Kamp <wmkamp@datakamp.de> | 2013-03-11 16:35:42 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-15 17:51:48 +0100 |
| commit | 9ae1eb6961b483c9905423fb113100a8038b4507 (patch) | |
| tree | 68d440ec8ed012778e4ef8404c41bd666d4e310a /3rdparty/stm | |
| parent | 8d629c14eb776ce6e243218bb554a335dc0f3672 (diff) | |
| download | coreboot-9ae1eb6961b483c9905423fb113100a8038b4507.tar.gz coreboot-9ae1eb6961b483c9905423fb113100a8038b4507.tar.bz2 coreboot-9ae1eb6961b483c9905423fb113100a8038b4507.zip | |
Super I/O W83627DHG: Enable UART B by redirecting pins
Pins 78-85 are set to GPIO after power on or reset. To enable
UART B the pins must be redirected to it.
Look at W83627DHG databook version 1.4 page 185 Chip
(global) Control Register CR2C.
Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845
Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de>
Reviewed-on: http://review.coreboot.org/2626
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Diffstat (limited to '3rdparty/stm')
0 files changed, 0 insertions, 0 deletions