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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-11 18:26:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-14 11:36:09 +0000 |
| commit | 3af6aa10f7a439e97a5f7d159336b4a207a97c21 (patch) | |
| tree | 37f521bf43fe3f50237ac19ac5da9d65a69255e8 /3rdparty/vboot | |
| parent | 125c9cf98cba524d3f8259bc34dc4c3f515403b4 (diff) | |
| download | coreboot-3af6aa10f7a439e97a5f7d159336b4a207a97c21.tar.gz coreboot-3af6aa10f7a439e97a5f7d159336b4a207a97c21.tar.bz2 coreboot-3af6aa10f7a439e97a5f7d159336b4a207a97c21.zip | |
arch/x86: Optimise PCI IO config accessor
By design only 'reg' parameter can have the two least-
significant bits set. As 'reg' is often a constant,
'0xCFC + (reg & 3)' resolves to an immediate value
already at buildtime, unlike (addr & 3) which depends
of a constant (but non-immediate) value of 'dev' in
ramstage.
Change-Id: I6e729fe800c92b1ce4994ad2b4203072fa75a958
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31754
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to '3rdparty/vboot')
0 files changed, 0 insertions, 0 deletions