mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`4.10

Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx:
Detect if the southbridge supports AHCI) but we forgot to update the
`chip.h` and devicetrees.

Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 3 insertions, 9 deletions

diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
index de63da2a5d3a..972dc5dc1fe8 100644
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -50,7 +50,6 @@ chip northbridge/intel/i945
 
 			register "gpe0_en" = "0"
 
-			register "ide_legacy_combined" = "0x0"
 			register "ide_enable_primary" = "0x1"
 			register "ide_enable_secondary" = "0x0"
 
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index c99455322b45..3135ac435267 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -54,7 +54,7 @@ chip northbridge/intel/i945
 			register "gpe0_en" = "0x00800106"
 			register "alt_gp_smi_en" = "0x0100"
 
-                        register "ide_legacy_combined" = "0x1"
+                        register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
                         register "ide_enable_primary" = "0x1"
                         register "ide_enable_secondary" = "0x0"
 
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
index 1c69613cbe56..f7e8ccc9a6c3 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -73,7 +73,6 @@ chip northbridge/intel/i945
 
 			register "gpe0_en" = "0"
 
-			register "ide_legacy_combined" = "0x0"
 			register "ide_enable_primary" = "0x1"
 			register "ide_enable_secondary" = "0x0"
 			register "c3_latency" = "85"
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index d24eb5d6ac3d..7045dbf8e11d 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -45,7 +45,6 @@ chip northbridge/intel/x4x		# Northbridge
       register "pirqf_routing" = "0x0b"
       register "pirqg_routing" = "0x0b"
       register "pirqh_routing" = "0x0b"
-      register "ide_legacy_combined" = "0x0"	# Combined mode broken
       register "ide_enable_primary" = "0x1"
       register "ide_enable_secondary" = "0x0"
       register "sata_ports_implemented" = "0x3"
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index 0c5962fea0c1..97f7a7b49d44 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -33,7 +33,6 @@ chip northbridge/intel/i945
 			#  2 SCI (if corresponding GPIO_EN bit is also set)
 			register "gpi13_routing" = "1"
 
-			register "ide_legacy_combined" = "0x0"
 			register "ide_enable_primary" = "0x1"
 			register "ide_enable_secondary" = "0x0"
 
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 573b9c80edb4..c01465c4e73f 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -47,7 +47,6 @@ chip northbridge/intel/i945
 			register "gpi13_routing" = "1"
 			register "gpe0_en" = "0x20000601"
 
-                        register "ide_legacy_combined" = "0x0"
                         register "ide_enable_primary" = "0x1"
                         register "ide_enable_secondary" = "0x0"
 			register "c3_latency" = "85"
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index cd7929c31a87..5db7551d1256 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -33,7 +33,7 @@ chip northbridge/intel/i945
 			#  2 SCI (if corresponding GPIO_EN bit is also set)
 			register "gpi13_routing" = "1"
 
-			register "ide_legacy_combined" = "0x1"
+			register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
 			register "ide_enable_primary" = "0x1"
 			register "ide_enable_secondary" = "0x1"
 			register "c3_latency" = "85"
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index 3ba9d2c33126..0ceef6a2fd46 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -58,7 +58,7 @@ chip northbridge/intel/i945
 			register "docking_supported" = "1"
 			register "p_cnt_throttling_supported" = "1"
 
-			register "ide_legacy_combined" = "0x1"
+			register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
 			register "ide_enable_primary" = "0x1"
 			register "ide_enable_secondary" = "0x0"
 
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index 8909f50bc12e..4e78c30db247 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -68,7 +68,6 @@ struct southbridge_intel_i82801gx_config {
 	uint16_t alt_gp_smi_en;
 
 	/* IDE configuration */
-	uint32_t ide_legacy_combined;
 	uint32_t ide_enable_primary;
 	uint32_t ide_enable_secondary;
 	enum sata_mode sata_mode;