diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-05-07 21:25:17 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-10 14:14:24 +0000 |
| commit | 1f44efc2028575fcf940ef188f62bf3730a3d81d (patch) | |
| tree | fb22629e3e3f99a3845eb0d9b67fb8bde2f6889b | |
| parent | 4caa05e4ce566473d408831f06d958789f55c245 (diff) | |
| download | coreboot-1f44efc2028575fcf940ef188f62bf3730a3d81d.tar.gz coreboot-1f44efc2028575fcf940ef188f62bf3730a3d81d.tar.bz2 coreboot-1f44efc2028575fcf940ef188f62bf3730a3d81d.zip | |
soc/intel/skylake: Set proper defaults in chipset devicetree
LPC, P2SB and Power Management controller are always needed. Thus,
enable them by default.
Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
| -rw-r--r-- | src/soc/intel/skylake/chipset.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb index 428db67d3a6a..37100f037bc2 100644 --- a/src/soc/intel/skylake/chipset.cb +++ b/src/soc/intel/skylake/chipset.cb @@ -59,9 +59,9 @@ chip soc/intel/skylake device pci 1e.4 alias emmc off end # EMMC device pci 1e.5 alias sdio off end # SDIO device pci 1e.6 alias sdxc off end # SDXC - device pci 1f.0 alias lpc_espi off end # LPC Interface - device pci 1f.1 alias p2sb off end # P2SB - device pci 1f.2 alias pmc off end # Power Management Controller + device pci 1f.0 alias lpc_espi on end # LPC Interface + device pci 1f.1 alias p2sb on end # P2SB + device pci 1f.2 alias pmc on end # Power Management Controller device pci 1f.3 alias hda off end # Intel HDA device pci 1f.4 alias smbus off end # SMBus device pci 1f.5 alias fast_spi off end # PCH SPI |