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| author | Raul E Rangel <rrangel@chromium.org> | 2021-05-04 15:42:09 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-09 18:09:53 +0000 |
| commit | fd7ed87746d763feff7d26dba9598b505e8750c1 (patch) | |
| tree | 49e79ef6e693f47daca4ea3355711db328a6a15b | |
| parent | 7b84b02492ec3ae1209c369f9149dd12e69d158a (diff) | |
| download | coreboot-fd7ed87746d763feff7d26dba9598b505e8750c1.tar.gz coreboot-fd7ed87746d763feff7d26dba9598b505e8750c1.tar.bz2 coreboot-fd7ed87746d763feff7d26dba9598b505e8750c1.zip | |
soc/amd/cezanne: Populate PCI_INTR registers
This uses the new FSP PCI methods to pull the routing table and populate
the pirq data structure.
BUG=b:184766519
TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fch.c | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 1d769be84dce..dafc26f4ef72 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -61,6 +61,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE + select SOC_AMD_COMMON_FSP_PCI select SSE2 select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 88265abb0496..028ffec17b7e 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -131,6 +131,12 @@ static void set_pci_irqs(void *unused) { /* Write PCI_INTR regs 0xC00/0xC01 */ write_pci_int_table(); + + /* pirq_data is consumed by `write_pci_cfg_irqs` */ + populate_pirq_data(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); } /* |