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| author | Raul E Rangel <rrangel@chromium.org> | 2022-02-24 11:49:52 -0700 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-26 00:09:27 +0000 |
| commit | 737ad67d122b24f8309ad76b66b5d7a26873eb39 (patch) | |
| tree | dc69a78aedbd7f78e96d6688c29582ce1eb40f78 | |
| parent | 5e0ed5016c8096a58b3d8758495c0969e0c1052c (diff) | |
| download | coreboot-737ad67d122b24f8309ad76b66b5d7a26873eb39.tar.gz coreboot-737ad67d122b24f8309ad76b66b5d7a26873eb39.tar.bz2 coreboot-737ad67d122b24f8309ad76b66b5d7a26873eb39.zip | |
soc/amd/common/psp_verstage: Add missing post codes on S0i3 resume
We print these out in the normal flow, so lets add them for S0i3 resume
as well.
BUG=b:221231786
TEST=Perform suspend/resume cycle on guybrush and verify we get the new
POST codes.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
| -rw-r--r-- | src/soc/amd/common/psp_verstage/psp_verstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 7359a44e52d5..05f0cdac3940 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -251,7 +251,11 @@ void Main(void) svc_get_boot_mode(&bootmode); if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) { psp_verstage_s0i3_resume(); + + post_code(POSTCODE_UNMAP_FCH_DEVICES); unmap_fch_devices(); + + post_code(POSTCODE_LEAVING_VERSTAGE); svc_exit(0); } |