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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-02-24 07:22:01 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-25 20:42:36 +0000 |
| commit | 92c2ccda0cab63b989582584392565fcc93d4def (patch) | |
| tree | 91f2d195ba5647c67052050a2317fe83bd0b2d1a | |
| parent | bd90a226a3ea0ecaa244dbc36be9fa1dabdb352a (diff) | |
| download | coreboot-92c2ccda0cab63b989582584392565fcc93d4def.tar.gz coreboot-92c2ccda0cab63b989582584392565fcc93d4def.tar.bz2 coreboot-92c2ccda0cab63b989582584392565fcc93d4def.zip | |
sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 9edbcf6aa7a9..4df47f3cf17d 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -48,7 +48,8 @@ void ibexpeak_setup_bars(void) outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); printk(BIOS_DEBUG, " done.\n"); - pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0, + (uintptr_t)DEFAULT_HECIBAR); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } |