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| author | Bill XIE <persmule@hardenedlinux.org> | 2023-01-29 09:55:19 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-08 19:19:43 +0000 |
| commit | 79a11950acfc55e6f7a2e9c673991c1dafc59f91 (patch) | |
| tree | 258f3044d454bb2448988e47506146895ef9c049 | |
| parent | 4d661eebe95b06acae7d99777ed36ba56a560112 (diff) | |
| download | coreboot-4.19_branch.tar.gz coreboot-4.19_branch.tar.bz2 coreboot-4.19_branch.zip | |
nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw4.19_branch
Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries.
This can restore s3 resume capability for Sandy Bridge platforms lost
after commit d165357ec37c ("sb,soc/intel: Use
register_new_ioapic_gsi0()").
Cherry-picked from
commit b184e6e0a1cc ("nb/intel/{sandybridge,haswell}: Generate IOAPIC
DMAR entries from hw").
Original-signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/72513
Original-reviewed-by: Nico Huber <nico.h@gmx.de>
Original-reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
| -rw-r--r-- | src/northbridge/intel/haswell/acpi.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/acpi.c | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 290dc1e92873..8d179aaa623f 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" @@ -38,8 +39,9 @@ static unsigned long acpi_fill_dmar(unsigned long current) const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, + PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index c2f6eae0e7da..8be161ec05d1 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "sandybridge.h" @@ -42,8 +43,9 @@ static unsigned long acpi_fill_dmar(unsigned long current) const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, + PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) |