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| author | Marc Jones <marcj303@gmail.com> | 2009-01-23 22:18:24 +0000 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2009-01-23 22:18:24 +0000 |
| commit | 70b7967bb64a802b984dd6b4c6bc8329da68c0a1 (patch) | |
| tree | 22b17e032afd91499c0eaf7dc7a0723ccc700204 | |
| parent | d6cf2da867a1a739c6188d8afa54c883cfd2082d (diff) | |
| download | coreboot-70b7967bb64a802b984dd6b4c6bc8329da68c0a1.tar.gz coreboot-70b7967bb64a802b984dd6b4c6bc8329da68c0a1.tar.bz2 coreboot-70b7967bb64a802b984dd6b4c6bc8329da68c0a1.zip | |
Fix rs690 bug about GPPSB configuration.
Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Zheng Bao <Zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1123 f3766cd6-281f-0410-b1cd-43a5c92072e9
| -rw-r--r-- | southbridge/amd/rs690/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/southbridge/amd/rs690/pcie.c b/southbridge/amd/rs690/pcie.c index 799a4ab20e2b..e2f54ecc074b 100644 --- a/southbridge/amd/rs690/pcie.c +++ b/southbridge/amd/rs690/pcie.c @@ -135,8 +135,8 @@ static void switching_gpp_configurations(struct device * nb_dev, struct device * /* sets desired GPPSB configurations, bit4-7 */ reg = nbmisc_read_index(nb_dev, 0x67); - reg &= 0xff0f; /* clean */ - reg |= cfg->gpp_configuration; + reg &= 0xffffff0f; /* clean */ + reg |= cfg->gpp_configuration << 4; nbmisc_write_index(nb_dev, 0x67, reg); /* read bit14 and write back its inverst value */ |