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| author | Sean Rhodes <sean@starlabs.systems> | 2024-02-13 20:44:52 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-19 17:42:44 +0000 |
| commit | 00b81adfedd0f61beb3fd7f3775f5d215b6307c4 (patch) | |
| tree | f9399d44aab58601ffabae5d533cd20cedd5da37 | |
| parent | ccd18d1bb4a0d8a689c508833f2af21f92a4a8ac (diff) | |
| download | coreboot-00b81adfedd0f61beb3fd7f3775f5d215b6307c4.tar.gz coreboot-00b81adfedd0f61beb3fd7f3775f5d215b6307c4.tar.bz2 coreboot-00b81adfedd0f61beb3fd7f3775f5d215b6307c4.zip | |
soc/intel/alderlake: Include ADL-N ID 5 0x4618
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
| -rw-r--r-- | src/mainboard/intel/adlrvp/ramstage.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/report_platform.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/cpu.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/vr_config.c | 2 |
6 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 3ffc35be95e2..7a6bb5d04cbe 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -25,6 +25,7 @@ const struct cpu_power_limits limits[] = { { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, { PCI_DID_INTEL_ADL_N_ID_4, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, 3000, 6000, 25000, 25000, 78000 }, }; WEAK_DEV_PTR(dptf_policy); diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index c4863b9703df..2a4f31a0d150 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -61,6 +61,7 @@ static struct { { PCI_DID_INTEL_ADL_N_ID_2, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_5, "Alderlake-N" }, { PCI_DID_INTEL_ADL_S_ID_1, "Alderlake-S (8+8)" }, { PCI_DID_INTEL_ADL_S_ID_2, "Alderlake-S" }, { PCI_DID_INTEL_ADL_S_ID_3, "Alderlake-S (8+4)" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 2f94db65df66..437d675ecfe2 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -153,6 +153,7 @@ static const struct { { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index fafd54d9f15d..2d25bb653a0f 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -240,6 +240,7 @@ enum adl_cpu_type get_adl_cpu_type(void) PCI_DID_INTEL_ADL_N_ID_2, PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, + PCI_DID_INTEL_ADL_N_ID_5, }; const uint16_t rpl_hx_mch_ids[] = { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5edfbcc78184..cb5459868a3a 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -539,6 +539,7 @@ static uint16_t get_vccin_aux_imon_iccmax(void) case PCI_DID_INTEL_ADL_N_ID_2: case PCI_DID_INTEL_ADL_N_ID_3: case PCI_DID_INTEL_ADL_N_ID_4: + case PCI_DID_INTEL_ADL_N_ID_5: return ICC_MAX_ID_ADL_N_MA; case PCI_DID_INTEL_ADL_S_ID_1: case PCI_DID_INTEL_ADL_S_ID_3: diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 3467bdd13914..911e1ddfebd1 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -127,6 +127,7 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, @@ -187,6 +188,7 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |