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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-06-29 11:32:01 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-04 14:07:44 +0000 |
| commit | 073779b5efc8c055185962cc55fabbed5433fba0 (patch) | |
| tree | 0688cc263e069001660ef48da9d152cfae4daf7c | |
| parent | 23ddcb0bc4a952e773cf62fefc499bbbe490f7af (diff) | |
| download | coreboot-073779b5efc8c055185962cc55fabbed5433fba0.tar.gz coreboot-073779b5efc8c055185962cc55fabbed5433fba0.tar.bz2 coreboot-073779b5efc8c055185962cc55fabbed5433fba0.zip | |
soc/intel/alderlake: Hook up ADL-P and ADL-S public FSP
Update 3rdparty/fsp submodule to include AlderLake FSP.
Hook up the Kconfig settings to point to Fsp.fd and headers for
ADL-S and ADL-P platforms which the FSP has been published for.
The FSP binaries are compliant with the specification revision 2.3
so update these settings accordingly.
Although FSP header is v2.3 compliant, the features set of the FSP
v2.3 is not being met.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| m--------- | 3rdparty/fsp | 0 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 12 |
2 files changed, 9 insertions, 3 deletions
diff --git a/3rdparty/fsp b/3rdparty/fsp -Subproject c607bab63b0c6f31c2b06b50ceecadf24ca428e +Subproject 3853be02e71adb8f87d2c792b9f3f855b798e42 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f6ef7a7e042c..117bf064eb03 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -26,12 +26,16 @@ config SOC_INTEL_ALDERLAKE_PCH_N config SOC_INTEL_ALDERLAKE_PCH_P bool select SOC_INTEL_ALDERLAKE + select HAVE_INTEL_FSP_REPO + select PLATFORM_USES_FSP2_3 help Choose this option if your mainboard has a PCH-P chipset. config SOC_INTEL_ALDERLAKE_PCH_S bool select SOC_INTEL_ALDERLAKE + select HAVE_INTEL_FSP_REPO + select PLATFORM_USES_FSP2_3 help Choose this option if your mainboard has a PCH-S chipset. @@ -70,8 +74,7 @@ config CPU_SPECIFIC_OPTIONS select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_2 if !SOC_INTEL_ALDERLAKE_PCH_S - select PLATFORM_USES_FSP2_3 if SOC_INTEL_ALDERLAKE_PCH_S + select PLATFORM_USES_FSP2_2 select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE @@ -357,12 +360,15 @@ config FSP_HEADER_PATH string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE + default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" + default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT int "Debug Consent for ADL" |