diff options
| author | Nico Huber <nico.h@gmx.de> | 2019-05-29 23:13:47 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-03 13:26:00 +0000 |
| commit | 10ed868d1999e4bd69efd8b86093bd953b8f8827 (patch) | |
| tree | bd8e766fed982bc7e6dc800033819ef74a172a95 | |
| parent | 2deb5fb3b07e07ee3d0d142723e2a25f5982d417 (diff) | |
| download | coreboot-10ed868d1999e4bd69efd8b86093bd953b8f8827.tar.gz coreboot-10ed868d1999e4bd69efd8b86093bd953b8f8827.tar.bz2 coreboot-10ed868d1999e4bd69efd8b86093bd953b8f8827.zip | |
soc/intel/{skl,cnl,icl}: Drop soc_uart_set_legacy_mode()
This is never called: The only calling path is guarded by both
!DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the
latter selects the former.
If somebody figures out how this is supposed to be used, we can
easily revive the implementation.
Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33093
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/cannonlake/uart.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/icelake/uart.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/skylake/uart.c | 15 |
3 files changed, 0 insertions, 45 deletions
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 2bd906adf894..7174a9a58f8a 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -24,10 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, @@ -54,17 +50,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 2bd906adf894..7174a9a58f8a 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -24,10 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, @@ -54,17 +50,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 1b2a7428df82..8b7c99eae526 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -24,10 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - /* UART pad configuration. Support RXD and TXD for now. */ const struct uart_gpio_pad_config uart_gpio_pads[] = { { @@ -55,17 +51,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* |