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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-11-09 14:53:31 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-05-22 06:12:00 +0000 |
| commit | 115aa9421db618f1e2f8f4161da4da3f0b37a849 (patch) | |
| tree | 2f619d095ec20768dc58412cf05b5420ac662546 | |
| parent | 60ee6fa398a110254235b0f9489b153d70a1ae84 (diff) | |
| download | coreboot-115aa9421db618f1e2f8f4161da4da3f0b37a849.tar.gz coreboot-115aa9421db618f1e2f8f4161da4da3f0b37a849.tar.bz2 coreboot-115aa9421db618f1e2f8f4161da4da3f0b37a849.zip | |
mb/msi/ms7d25: Disable PCIe hotplug
The support for the board has stabilized and PCIe ports have been
tested with many devices. Although hotplug is not commonly used
and it seems pointless to keep it enabled, so disable it.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I338c55cb57d971badd08235b71626a710fafb829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
| -rw-r--r-- | src/mainboard/msi/ms7d25/devicetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index e175afa45433..91b55bb3989c 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -98,7 +98,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(2)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -141,7 +141,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 10, .clk_req = 10, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -152,7 +152,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(2)]" = "{ .clk_src = 17, .clk_req = 17, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" @@ -174,7 +174,7 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 15, .clk_req = 15, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_aspm = ASPM_L0S_L1, }" |