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authorJeremy Compostella <jeremy.compostella@intel.com>2023-03-13 10:55:21 -0700
committerNick Vaccaro <nvaccaro@google.com>2023-03-31 20:04:43 +0000
commit11f2f88a277124713f7b0023f078fcc2e1a98c32 (patch)
tree0a5266ccb31091793d09176ac9fd4bb25a332d7e
parente7a1204f26fe3628de99b4ab4e3f32916565b95c (diff)
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mb/google/brya: Enable asynchronous End-Of-Post
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/brya/Kconfig1
-rw-r--r--src/soc/intel/alderlake/Kconfig2
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 2976ae21653c..00804009943f 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -32,6 +32,7 @@ config BOARD_GOOGLE_BRYA_COMMON
select PMC_IPC_ACPI_INTERFACE
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_CSE_LITE_SKU
+ select SOC_INTEL_CSE_SEND_EOP_ASYNC
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE
select SOC_INTEL_CRASHLOG
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1bc84ce1717c..2887439d2085 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -122,7 +122,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
- select SOC_INTEL_CSE_SEND_EOP_LATE
+ select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON
select SOC_INTEL_CSE_SET_EOP
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select HAVE_INTEL_COMPLIANCE_TEST_MODE