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| author | Sean Rhodes <sean@starlabs.systems> | 2024-01-22 15:22:25 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-21 14:28:52 +0000 |
| commit | 12781b64cb83bfac6f679f5bdfddf5e2423258cb (patch) | |
| tree | 770dbe322a65275d1e4c96df1e76bb3ffe917a71 | |
| parent | a2f47bbd93117063130b3bd595bcfcde66ef53b2 (diff) | |
| download | coreboot-12781b64cb83bfac6f679f5bdfddf5e2423258cb.tar.gz coreboot-12781b64cb83bfac6f679f5bdfddf5e2423258cb.tar.bz2 coreboot-12781b64cb83bfac6f679f5bdfddf5e2423258cb.zip | |
soc/intel/alderlake: Include ADL-N ID 5
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/alderlake/vr_config.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 911e1ddfebd1..6718e89a44e4 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -249,6 +249,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -309,6 +310,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, |