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authorIvy Jian <ivy_jian@compal.corp-partner.google.com>2021-08-12 12:06:38 +0800
committerNick Vaccaro <nvaccaro@google.com>2021-08-13 18:04:26 +0000
commit13bf4dde29d9ac0b3142a5558d9663f9734fc2c1 (patch)
treeb47d67884e31cc15897ef615665a499a815186cb
parentbcc74afa73609f1555fca146196ef3179ae841f4 (diff)
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mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5
Tune the USB phy settings to update TXVREFTUNE0/COMPDISTUNE0 to higher value for USB port 5 (Type-A). BUG=b:194053549 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56925 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index f9a1201d68e2..c707c0fcc3b9 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -118,13 +118,13 @@ chip soc/amd/cezanne
.txrestune = 1,
},
.Usb2PhyPort[5] = {
- .compdstune = 3,
+ .compdstune = 5,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 1,
.txpreemppulsetune = 0,
.txrisetune = 1,
- .txvreftune = 6,
+ .txvreftune = 9,
.txhsxvtune = 3,
.txrestune = 1,
},