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| author | Werner Zeh <werner.zeh@siemens.com> | 2022-11-07 07:50:51 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-09 14:19:15 +0000 |
| commit | 14612f698c1ec76555ebe4c89ca771795450dff1 (patch) | |
| tree | c588b8d018f8dcccab02fd3b5ed85a297b997f42 | |
| parent | 6b4a1ab82a49c9288f7964b9c1836729dcc340a6 (diff) | |
| download | coreboot-14612f698c1ec76555ebe4c89ca771795450dff1.tar.gz coreboot-14612f698c1ec76555ebe4c89ca771795450dff1.tar.bz2 coreboot-14612f698c1ec76555ebe4c89ca771795450dff1.zip | |
soc/intel/elkhartlake: Correct I2C base clock to 100 MHz
According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).
This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.
Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/soc/intel/elkhartlake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 4343e8557042..8e3dc1196a26 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -151,7 +151,7 @@ config CPU_XTAL_HZ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default 133 + default 100 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int |