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| author | Won Chung <wonchung@google.com> | 2022-05-27 22:37:10 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-08 22:03:56 +0000 |
| commit | 18c2720c7f77f730872528df47e39d6ef5b77613 (patch) | |
| tree | d4dfbf08e71d2506eac6c84de202b73d2badae93 | |
| parent | 970554f90d188cf4a0f97a5fb9ab8210ee420e41 (diff) | |
| download | coreboot-18c2720c7f77f730872528df47e39d6ef5b77613.tar.gz coreboot-18c2720c7f77f730872528df47e39d6ef5b77613.tar.bz2 coreboot-18c2720c7f77f730872528df47e39d6ef5b77613.zip | |
mb/google/brya/var/brask: Add ACPI _PLD custom values
This patch uses ACPI _PLD macros to add custom values for USB ports.
C2 C0 A3 A2
+----------------+
| REAR |
| |
| |
| |
| FRONT |
+----------------+
C1 A1 A0
BUG=b:232298007
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I6a9ead24ef9d73bc0b09301cf641009ced0c6810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64732
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/brask/overridetree.cb | 42 |
1 files changed, 28 insertions, 14 deletions
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 17c9e86a3ee9..03bdb533cf2f 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -202,19 +202,22 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on end end end @@ -226,19 +229,22 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -249,25 +255,29 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A3 (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(5, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))" device ref usb2_port6 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A2 (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(6, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))" device ref usb2_port7 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A1 (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 1))" device ref usb2_port8 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -280,25 +290,29 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A1 (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 1))" device ref usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A2 (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(6, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))" device ref usb3_port3 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A3 (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(5, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))" device ref usb3_port4 on end end end |