soc/intel/tigerlake: Implement SoC sleep state array

Copied from Alderlake implementation, modified as needed for Tigerlake.
Device names missing from soc_acpi_name() were added as well.

TEST=build/boot Win11, Linux on google/volteer (drobit).

Change-Id: I34999891ea0d386328698109b6315d481de7c43a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78521
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

2 files changed, 68 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 9ff6e1885726..5c4c838a6f07 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -160,6 +160,65 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 
+static struct min_sleep_state min_pci_sleep_states[] = {
+	{ SA_DEVFN_ROOT,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_IGD,		ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_IPU,		ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_CPU_PCIE,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TBT0,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TBT1,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TBT2,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TBT3,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_GNA,		ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TCSS_XHCI,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TCSS_XDCI,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TCSS_DMA0,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_TCSS_DMA1,	ACPI_DEVICE_SLEEP_D3 },
+	{ SA_DEVFN_VMD,		ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_THC0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_THC1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_XHCI,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_USBOTG,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_SRAM,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_CNVI_WIFI,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_I2C0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_I2C1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_I2C2,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_I2C3,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_CSE,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_SATA,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_I2C4,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_I2C5,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_UART2,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_PCIE1,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE2,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE3,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE4,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE5,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE6,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE7,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE8,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE9,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE10,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE11,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PCIE12,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_UART0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_UART1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_GSPI0,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_GSPI1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_ESPI,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_PMC,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_HDA,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_SPI,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCH_DEVFN_GBE,	ACPI_DEVICE_SLEEP_D3 },
+};
+
+struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
+{
+	*size = ARRAY_SIZE(min_pci_sleep_states);
+	return min_pci_sleep_states;
+}
+
 uint32_t soc_read_sci_irq_select(void)
 {
 	return read32p(soc_read_pmc_base() + IRQ_REG);
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 024763dd7f8b..dd2467927342 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -77,13 +77,18 @@ const char *soc_acpi_name(const struct device *dev)
 	case SA_DEVFN_PEG1:		return "PEG1";
 	case SA_DEVFN_PEG2:		return "PEG2";
 	case SA_DEVFN_PEG3:		return "PEG3";
+	case SA_DEVFN_IGD:		return "GFX0";
+	case SA_DEVFN_TCSS_XHCI:	return "TXHC";
 	case SA_DEVFN_TCSS_XDCI:	return "TXDC";
+	case SA_DEVFN_TCSS_DMA0:	return "TDM0";
+	case SA_DEVFN_TCSS_DMA1:	return "TDM1";
 	case SA_DEVFN_TBT0:		return "TRP0";
 	case SA_DEVFN_TBT1:		return "TRP1";
 	case SA_DEVFN_TBT2:		return "TRP2";
 	case SA_DEVFN_TBT3:		return "TRP3";
 	case SA_DEVFN_IPU:		return "IPU0";
 	case SA_DEVFN_GNA:		return "GNA";
+	case SA_DEVFN_DPTF:		return "TCPU";
 	case PCH_DEVFN_ISH:		return "ISHB";
 	case PCH_DEVFN_XHCI:		return "XHCI";
 	case PCH_DEVFN_I2C0:		return "I2C0";
@@ -125,9 +130,13 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_GSPI1:		return "SPI1";
 	case PCH_DEVFN_GSPI2:		return "SPI2";
 	case PCH_DEVFN_GSPI3:		return "SPI3";
+	case PCH_DEVFN_ESPI:		return "LPCB";
 	case PCH_DEVFN_HDA:		return "HDAS";
 	case PCH_DEVFN_SMBUS:		return "SBUS";
 	case PCH_DEVFN_GBE:		return "GLAN";
+	case PCH_DEVFN_SRAM:		return "SRAM";
+	case PCH_DEVFN_SPI:		return "FSPI";
+	case PCH_DEVFN_CSE:		return "HEC1";
 	}
 
 	return NULL;