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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2022-01-20 14:01:34 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-03 16:26:26 +0000 |
| commit | 1d886639ce680010a21e64d7122dfcfa92a9f505 (patch) | |
| tree | c57b01c9183239308da26094729057213c75d903 | |
| parent | 46c9f761d416c3393b7d4afaeb573aacda6f4bb3 (diff) | |
| download | coreboot-1d886639ce680010a21e64d7122dfcfa92a9f505.tar.gz coreboot-1d886639ce680010a21e64d7122dfcfa92a9f505.tar.bz2 coreboot-1d886639ce680010a21e64d7122dfcfa92a9f505.zip | |
mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
Gimble does not use WWAN and TCP Port 1 according to the schematics.
Hence disabling it.
BUG=b:216533766
TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/overridetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 23071fe97a61..408d380ce21b 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -38,6 +38,7 @@ chip soc/intel/alderlake register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -121,6 +122,7 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref pcie_rp6 off end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" |