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author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-06-19 14:59:06 -0700 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-06-22 07:35:42 +0200 |
commit | 1e2500e948750270011b133203be0fe1dbcba827 (patch) | |
tree | 001b62e8aca6e891a079daa3e3750bbb15852eed | |
parent | 83fa169101e732b35a36f19624979b378a06f3f5 (diff) | |
download | coreboot-1e2500e948750270011b133203be0fe1dbcba827.tar.gz coreboot-1e2500e948750270011b133203be0fe1dbcba827.tar.bz2 coreboot-1e2500e948750270011b133203be0fe1dbcba827.zip |
device: DDR3 generic code 64bit fix
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I5ff309948c36289eedeb8a18030cdd2b4c337690
Reviewed-on: http://review.coreboot.org/10595
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
-rw-r--r-- | src/include/device/dram/ddr3.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 10924a2680ac..295ea2581db8 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -186,7 +186,7 @@ void dram_print_spd_ddr3(const dimm_attr * dimm); * * Should be useful when doing an MRS to the DIMM */ -static inline u32 volatile_read(volatile u32 addr) +static inline u32 volatile_read(volatile uintptr_t addr) { volatile u32 result; result = *(volatile u32 *)addr; |