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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-26 10:44:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-30 08:31:22 +0000 |
| commit | 1f30de08f67a534eac5d30b414f231c1166a817e (patch) | |
| tree | f965bb6c5467f8fb4ffb06dcb9144077eb1edb35 | |
| parent | e0ad1fa7c82e0a31ec628dd43cbd915550b04f3d (diff) | |
| download | coreboot-1f30de08f67a534eac5d30b414f231c1166a817e.tar.gz coreboot-1f30de08f67a534eac5d30b414f231c1166a817e.tar.bz2 coreboot-1f30de08f67a534eac5d30b414f231c1166a817e.zip | |
soc/intel/cannonlake: set FSP param to enable or skip GOP
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.
Change-Id: I7f7b2c688e46534046dc0976458c4c96614100b0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 74884fde1f8c..0713ef4604e4 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -460,6 +460,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SpiFlashCfgLockDown = 1; #endif } + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; } /* Mainboard GPIO Configuration */ |