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| author | Tarun Tuli <taruntuli@google.com> | 2023-02-13 16:41:36 +0000 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-02-15 02:14:15 +0000 |
| commit | 2072296330b6a79b5a502361a44d64302ee671dd (patch) | |
| tree | 26f8a5c6b1c71a864cac6f2237a8fdd3cfb1c15b | |
| parent | 944aff2635314e7ae7da7f7d8dfc16fc75822ec1 (diff) | |
| download | coreboot-2072296330b6a79b5a502361a44d64302ee671dd.tar.gz coreboot-2072296330b6a79b5a502361a44d64302ee671dd.tar.bz2 coreboot-2072296330b6a79b5a502361a44d64302ee671dd.zip | |
mb/google/brya/agah: Adjust i2c1 and i2c2 timing Parameters for 400KHz
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.
For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.
BUG=b:264704732
TEST=Verified all timings meet spec now
Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/overridetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 53c60c17f313..52b9fcddbe45 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -20,9 +20,15 @@ chip soc/intel/alderlake }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 300, + .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 300, + .data_hold_time_ns = 50, }, .i2c[3] = { .early_init = 1, |