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authorSubrata Banik <subratabanik@google.com>2022-01-10 09:15:56 +0000
committerFelix Held <felix-coreboot@felixheld.de>2022-01-21 16:10:46 +0000
commit25387927c052aadd07746723e6cff10ab2b40d29 (patch)
tree9bd9437b041b9e31c4b0576bd965808cb84b8ad7
parent6a4f5739c8cf2ede8e9b6298a610b60621152eca (diff)
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soc/intel/common/gpio: Add PCH `Pad Configuration Lock` options
This patch provides the possible options for PCH to allow `Pad Configuration Lock`. `SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI` config is for Tiger Lake Point (TGP) and Alder Lake Point (ADP) PCH. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf35893ab613b154a1073060081a09e561ffe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
-rw-r--r--src/soc/intel/common/block/gpio/Kconfig15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig
index c94654535587..03a3b092c0dc 100644
--- a/src/soc/intel/common/block/gpio/Kconfig
+++ b/src/soc/intel/common/block/gpio/Kconfig
@@ -36,4 +36,19 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
bool
default n
+config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
+ bool
+ default n
+ help
+ From TGL PCH onwards,`Pad Configuration Lock` can only be set or cleared
+ using non-posted sideband write.
+
+config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR
+ bool
+ default n
+ depends on !SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
+ help
+ SoC user to select this config if `Pad Configuration Lock` can only be set or
+ cleared using private configuration register (PCR) write.
+
endif