sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible

TEST=boot PC Engines apu1 and apu2 and launch Debian Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

9 files changed, 50 insertions, 63 deletions

diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index 639a5e8764ef..090a85288b5c 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -17,6 +17,7 @@
 #define _HUDSON_EARLY_SETUP_C_
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <amdblocks/acpimmio.h>
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index 1d63c1e36ac7..934d1e95da51 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -14,6 +14,7 @@
  */
 
 #include "imc.h"
+#include <amdblocks/acpimmio.h>
 #include <device/mmio.h>
 #include <Porting.h>
 #include <AGESA.h>
@@ -22,24 +23,22 @@
 #include <Proc/Fch/Common/FchCommonCfg.h>
 #include <Proc/Fch/FchPlatform.h>
 
-#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE)
-
 void imc_reg_init(void)
 {
 	/* Init Power Management Block 2 (PM2) Registers.
 	 * Check BKDG for AMD Family 16h for details. */
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06);
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06);
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7);
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);
+	pm2_write8(0, 0x06);
+	pm2_write8(1, 0x06);
+	pm2_write8(2, 0xf7);
+	pm2_write8(3, 0xff);
+	pm2_write8(4, 0xff);
 
 #if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff);
-	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);
+	pm2_write8(0x10, 0x06);
+	pm2_write8(0x11, 0x06);
+	pm2_write8(0x12, 0xf7);
+	pm2_write8(0x13, 0xff);
+	pm2_write8(0x14, 0xff);
 #endif
 
 #if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c
index 8eb36f46ee6f..9ddae38c5b7d 100644
--- a/src/southbridge/amd/agesa/hudson/smbus_spd.c
+++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <console/console.h>
@@ -126,16 +127,9 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
 	return 0;
 }
 
-static void writePmReg (int reg, int data)
-{
-	__outbyte (0xCD6, reg);
-	__outbyte (0xCD7, data);
-}
-
 static void setupFch (int ioBase)
 {
-	writePmReg (0x2D, ioBase >> 8);
-	writePmReg (0x2C, ioBase | 1);
+	pm_write16(0x2c, ioBase | 1);
 	__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
 }
 
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 5decebfac47c..6e0b54434cfb 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -83,7 +83,6 @@ static void enable_spi_fast_mode(void)
 static void enable_clocks(void)
 {
 	u32 reg32;
-	volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
 
 	// Program SB800 MiscClkCntrl register to configure clock output on the
 	// 14M_25M_48M_OSC ball usually used for the Super-I/O.
@@ -91,12 +90,12 @@ static void enable_clocks(void)
 	// which is the SB800's power up default.  We could switch back to 14
 	// in the mainboard's romstage.c, but then the clock frequency would
 	// change twice.
-	reg32 = *acpi_mmio;
+	reg32 = misc_read32(0x40);
 	reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default)
 #if !CONFIG(SUPERIO_WANTS_14MHZ_CLOCK)
 	reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz
 #endif
-	*acpi_mmio = reg32;
+	misc_write32(0x40, reg32);
 }
 
 void bootblock_early_southbridge_init(void)
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 48829578e179..2ee4d40230b0 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include "SBPLATFORM.h"
 #include "sb_cimx.h"
 #include "cfg.h"		/*sb800_cimx_config*/
@@ -41,9 +42,7 @@ void sb_Poweron_Init(void)
  */
 void sb800_clk_output_48Mhz(void)
 {
-	/* AcpiMMioDecodeEn */
-	RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
 
-	*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
-	*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
+	misc_write32(0x40, misc_read32(0x40) & (~5));
+	misc_write32(0x40, misc_read32(0x40) | 2);
 }
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 4233a6ff0da8..d6003bede2a7 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-
+#include <amdblocks/acpimmio.h>
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci.h>		/* device_operations */
@@ -400,9 +400,9 @@ static void sb800_enable(struct device *dev)
 		 *              to function as GPIO {GPIO 35:0}.
 		 */
 		if (!sb_chip->disconnect_pcib && dev->enabled)
-			RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
+			pm_write8(0xea, pm_read8(0xea) & 0xfe);
 		else
-			RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);
+			pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
 		break;
 
 	case PCI_DEVFN(0x14, 6): /* 0:14:6 GEC */
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 191a96c7d432..fe7511523342 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -18,6 +18,7 @@
 
 #include <assert.h>
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
@@ -36,18 +37,17 @@ void configure_hudson_uart(void)
 {
 	u8 byte;
 
-	byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 +
-				CONFIG_UART_FOR_CONSOLE * sizeof(u16)));
-	byte |= 1 << 3;
-	write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 +
-			CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte);
-	byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62));
+	byte = aoac_read8(FCH_AOAC_REG56 +
+			  CONFIG_UART_FOR_CONSOLE * sizeof(u16)));
 	byte |= 1 << 3;
-	write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte);
-	write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
-	write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
-	write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
-	write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
+	aoac_write8(FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * sizeof(u16)),
+		    byte);
+
+	aoac_write8(FCH_AOAC_REG62, aoac_read8(FCH_AOAC_REG62) | (1 << 3));
+	iomux_write8(0x89, 0); /* UART0_RTS_L_EGPIO137 */
+	iomux_write8(0x8a, 0); /* UART0_TXD_EGPIO138 */
+	iomux_write8(0x8e, 0); /* UART1_RTS_L_EGPIO142 */
+	iomux_write8(0x8f, 0); /* UART1_TXD_EGPIO143 */
 
 	udelay(2000);
 	write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88),
@@ -229,11 +229,11 @@ void hudson_clk_output_48Mhz(void)
 	 * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
 	 * 48Mhz will be on ball AP13 (FT3b package)
 	 */
-	ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));
+	ctrl = misc_read32(FCH_MISC_REG40);
 
 	/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
 	ctrl &= (u32)~(1<<2);
-	write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);
+	misc_write32(FCH_MISC_REG40, ctrl);
 }
 
 static uintptr_t hudson_spibase(void)
diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c
index 6a01a764cb9f..3c6054d1478d 100644
--- a/src/southbridge/amd/pi/hudson/imc.c
+++ b/src/southbridge/amd/pi/hudson/imc.c
@@ -16,6 +16,7 @@
 #define __SIMPLE_DEVICE__
 
 #include "imc.h"
+#include <amdblocks/acpimmio.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
@@ -26,24 +27,24 @@
 #include <Proc/Fch/Fch.h>
 #include <Proc/Fch/FchPlatform.h>
 
-#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE)
-
 void imc_reg_init(void)
 {
 	u8 reg8;
 	/* Init Power Management Block 2 (PM2) Registers.
 	 * Check BKDG for AMD Family 16h for details. */
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff);
+	/* Init Power Management Block 2 (PM2) Registers.
+	 * Check BKDG for AMD Family 16h for details. */
+	pm2_write8(0, 0x06);
+	pm2_write8(1, 0x06);
+	pm2_write8(2, 0xf7);
+	pm2_write8(3, 0xff);
+	pm2_write8(4, 0xff);
 
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff);
+	pm2_write8(0x10, 0x06);
+	pm2_write8(0x11, 0x06);
+	pm2_write8(0x12, 0xf7);
+	pm2_write8(0x13, 0xff);
+	pm2_write8(0x14, 0xff);
 
 	reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4);
 	reg8 &= 0x8F;
diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c
index c49ccffc4db1..8523db5054be 100644
--- a/src/southbridge/amd/pi/hudson/smbus_spd.c
+++ b/src/southbridge/amd/pi/hudson/smbus_spd.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/acpimmio.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <device/device.h>
@@ -127,16 +128,9 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
 	return 0;
 }
 
-static void writePmReg (int reg, int data)
-{
-	__outbyte (0xCD6, reg);
-	__outbyte (0xCD7, data);
-}
-
 static void setupFch (int ioBase)
 {
-	writePmReg (0x2D, ioBase >> 8);
-	writePmReg (0x2C, ioBase | 1);
+	pm_write16(0x2c, ioBase | 1);
 	__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
 }