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| author | Tim Crawford <tcrawford@system76.com> | 2022-01-07 14:12:34 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 18:05:35 +0000 |
| commit | 2a404b599b3385b3246a2ee20844d2bc7a428035 (patch) | |
| tree | 64541bbb7f407c3c8e2615240e5454a67c4d0b80 | |
| parent | b65c3015b0c931b8ad7897a9835798cd97dbcf5b (diff) | |
| download | coreboot-2a404b599b3385b3246a2ee20844d2bc7a428035.tar.gz coreboot-2a404b599b3385b3246a2ee20844d2bc7a428035.tar.bz2 coreboot-2a404b599b3385b3246a2ee20844d2bc7a428035.zip | |
mb/system76: Enable SrcClk pin for CPU PCIe RPs
This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin
on CPU RP").
Previously, RTD3 expected a PCH index for the root port and did not work
with the CPU PCIe RP present on TGL, so SrcClk pin was disabled.
Set them now that RTD3 supports mapping the index for the CPU RP.
Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
6 files changed, 6 insertions, 12 deletions
diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 21f8141c5f92..4b7ad233ea81 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -113,8 +113,7 @@ chip soc/intel/tigerlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST# - # TODO: Support disable/enable CPU RP clock - register "srcclk_pin" = "-1" # SSD1_CLKREQ# + register "srcclk_pin" = "0" # SSD1_CLKREQ# device generic 0 on end end end diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 8bc74e34e151..81163b654793 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -113,8 +113,7 @@ chip soc/intel/tigerlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 - # TODO: Support disable/enable CPU RP clock - register "srcclk_pin" = "-1" # SSD1_CLKREQ# + register "srcclk_pin" = "0" # SSD1_CLKREQ# device generic 0 on end end end diff --git a/src/mainboard/system76/gaze16/variants/3050/overridetree.cb b/src/mainboard/system76/gaze16/variants/3050/overridetree.cb index c26b7d2fed84..32f0805ac0df 100644 --- a/src/mainboard/system76/gaze16/variants/3050/overridetree.cb +++ b/src/mainboard/system76/gaze16/variants/3050/overridetree.cb @@ -13,8 +13,7 @@ chip soc/intel/tigerlake register "enable_off_delay_ms" = "4" register "reset_delay_ms" = "10" register "reset_off_delay_ms" = "4" - # TODO: Support disable/enable CPU RP clock - register "srcclk_pin" = "-1" # GFX_CLKREQ0# + register "srcclk_pin" = "0" # GFX_CLKREQ0# device generic 0 on end end end diff --git a/src/mainboard/system76/gaze16/variants/3060/overridetree.cb b/src/mainboard/system76/gaze16/variants/3060/overridetree.cb index 7d5549935c55..881b2c5caf77 100644 --- a/src/mainboard/system76/gaze16/variants/3060/overridetree.cb +++ b/src/mainboard/system76/gaze16/variants/3060/overridetree.cb @@ -13,8 +13,7 @@ chip soc/intel/tigerlake register "enable_off_delay_ms" = "4" register "reset_delay_ms" = "10" register "reset_off_delay_ms" = "4" - # TODO: Support disable/enable CPU RP clock - register "srcclk_pin" = "-1" # PEG_CLKREQ# + register "srcclk_pin" = "9" # PEG_CLKREQ# device generic 0 on end end end diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index fc6c3b1774eb..e84c40549610 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -114,8 +114,7 @@ chip soc/intel/tigerlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly) - # TODO: Support disable/enable CPU RP clock - register "srcclk_pin" = "-1" # SSD2_CLKREQ# + register "srcclk_pin" = "3" # SSD2_CLKREQ# device generic 0 on end end end diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index d3cf5de9c9ce..65b6e874cdfb 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -99,8 +99,7 @@ chip soc/intel/tigerlake register "enable_off_delay_ms" = "4" register "reset_delay_ms" = "10" register "reset_off_delay_ms" = "4" - # TODO: Support disable/enable CPU RP clock - register "srcclk_pin" = "-1" # PEG_CLKREQ# + register "srcclk_pin" = "9" # PEG_CLKREQ# device generic 0 on end end end |