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| author | Felix Singer <felixsinger@posteo.net> | 2023-08-25 11:32:26 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-09-02 01:42:44 +0000 |
| commit | 2aeb6e405aea8740f87185158598f2af50390904 (patch) | |
| tree | 5601b6ae9350db892136d16ed4c97deed7f78801 | |
| parent | 53adf21174242a977aed984a4e9ff063be8f4f83 (diff) | |
| download | coreboot-2aeb6e405aea8740f87185158598f2af50390904.tar.gz coreboot-2aeb6e405aea8740f87185158598f2af50390904.tar.bz2 coreboot-2aeb6e405aea8740f87185158598f2af50390904.zip | |
soc/intel/cannonlake/Kconfig: Deduplicate selections
All of the SoCs in the cannonlake directory select the following
options. So move them to the common option SOC_INTEL_CANNONLAKE_BASE
in order to deduplicate selections.
* FSP_USES_CB_STACK
* HAVE_INTEL_FSP_REPO
* SOC_INTEL_CONFIGURE_DDI_A_4_LANES
Change-Id: I6ce5edb2ba2c138b44601b32c3ecba2e761136f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77447
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index b58dfd352611..80237f981085 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -13,11 +13,13 @@ config SOC_INTEL_CANNONLAKE_BASE select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSP_USES_CB_STACK select GENERIC_GPIO_LIB select HAVE_DPTF_EISA_HID select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT select HAVE_HYPERTHREADING + select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -58,6 +60,7 @@ config SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS @@ -72,30 +75,21 @@ config SOC_INTEL_CANNONLAKE_BASE config SOC_INTEL_COFFEELAKE bool select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK select HAVE_EXP_X86_64_SUPPORT - select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM select INTEL_CAR_NEM - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES config SOC_INTEL_WHISKEYLAKE bool select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK - select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM select INTEL_CAR_NEM_ENHANCED - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES config SOC_INTEL_COMETLAKE bool select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK - select HAVE_INTEL_FSP_REPO select INTEL_CAR_NEM_ENHANCED select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BASECODE_RAMTOP |