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| author | Tao Xia <xiatao5@huaqin.corp-partner.google.com> | 2021-06-15 16:15:08 +0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-30 04:53:15 +0000 |
| commit | 2ffd1bff2fd53adb232b3aedbf6ebb0eedce71fd (patch) | |
| tree | ef6410edbeb87a512bcc15728f3dc318a9c5a5c9 | |
| parent | 9d05cf11b5c938974500557e9717101cb656d01b (diff) | |
| download | coreboot-2ffd1bff2fd53adb232b3aedbf6ebb0eedce71fd.tar.gz coreboot-2ffd1bff2fd53adb232b3aedbf6ebb0eedce71fd.tar.bz2 coreboot-2ffd1bff2fd53adb232b3aedbf6ebb0eedce71fd.zip | |
mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0
This change adds fine-tuned USB2 PHY parameters for storo.
BUG=191089827
TEST=Built and verified USB2 eye diagram test result
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
| -rw-r--r-- | src/mainboard/google/dedede/variants/storo/overridetree.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index bcd094b48d6d..7ddadbded826 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -54,6 +54,15 @@ chip soc/intel/jasperlake }, }" + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # WWAN + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |