summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorRaul E Rangel <rrangel@chromium.org>2022-07-29 21:07:36 -0600
committerRaul Rangel <rrangel@chromium.org>2022-08-10 17:13:07 +0000
commit30edb46e8ca3b4994fda31c74e496910f8218818 (patch)
treed7a89029381a799f852f83c86e75752c67417476
parent74bce48f1d445053b217913df79a77dfe286e893 (diff)
downloadcoreboot-30edb46e8ca3b4994fda31c74e496910f8218818.tar.gz
coreboot-30edb46e8ca3b4994fda31c74e496910f8218818.tar.bz2
coreboot-30edb46e8ca3b4994fda31c74e496910f8218818.zip
mb/google/zork: Set vw_irq_polarity from low to high
The EC used on zork uses a level high interrupt. This change configures the polarity correctly. The eSPI config is baked into RO verstage. The zork ToT build doesn't use signed verstage since it's incompatible with the ToT version of vboot. This means we can safely switch the keyboard IRQ polarity. NOTE: Do not cherry pick this into the Zork firmware branch! BUG=b:160595155 TEST=On morphius verify keyboard works as correctly and no spurious interrupts are thrown on S0i3 resume. Also verified keyboard and mouse work correctly in windows. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb8
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb8
-rw-r--r--src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h1
-rw-r--r--src/mainboard/google/zork/variants/morphius/include/variant/ec.h1
4 files changed, 4 insertions, 14 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 69146041e82..68eb6ea5887 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -227,13 +227,7 @@ chip soc/amd/picasso
.oob_ch_en = 0,
.flash_ch_en = 0,
- /*
- * b/160595155 - These should really be ESPI_VW_IRQ_LEVEL_HIGH,
- * but eSPI gets configured in verstage which is in RO.
- * We have already locked RO for zork devices so we need
- * make it so x86 coreboot re-initializes the vw_irq_polarity.
- */
- .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12),
+ .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
}"
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 96e66aff1cb..4bb42dea1c9 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -225,13 +225,7 @@ chip soc/amd/picasso
.oob_ch_en = 0,
.flash_ch_en = 0,
- /*
- * b/160595155 - These should really be ESPI_VW_IRQ_LEVEL_HIGH,
- * but eSPI gets configured in verstage which is in RO.
- * We have already locked RO for zork devices so we need
- * make it so x86 coreboot re-initializes the vw_irq_polarity.
- */
- .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12),
+ .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
}"
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
index 46177fccfb8..d2ec79bef9f 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
@@ -63,6 +63,7 @@
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+#define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
/*
* Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in
diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h
index 3564d542cd3..fbcdf4e0f89 100644
--- a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h
+++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h
@@ -4,6 +4,7 @@
/* Enable PS/2 Mouse */
#define SIO_EC_ENABLE_PS2M
+#define SIO_EC_PS2M_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {12}
/* Enable DPTC support */
#define EC_ENABLE_AMD_DPTC_SUPPORT