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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-01 21:14:16 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-11 20:49:30 +0000 |
| commit | 320a3ab7d235adeeb0dd73e99995334cbe99ea9f (patch) | |
| tree | 600a4f0f0e0b6c698a25f7d7c4e04c3b17cd9ff2 | |
| parent | f0a44ae0eb329ba4c6f77f1635675ea042492be1 (diff) | |
| download | coreboot-320a3ab7d235adeeb0dd73e99995334cbe99ea9f.tar.gz coreboot-320a3ab7d235adeeb0dd73e99995334cbe99ea9f.tar.bz2 coreboot-320a3ab7d235adeeb0dd73e99995334cbe99ea9f.zip | |
soc/intel/cnl: add SLP_S0 residency register and enable LPIT support
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
boots without crashing with an INTERNAL_POWER_ERROR.
- Windows and Linux tested on google/akemi
- Linux tested on clevo/cml-u
Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046
Tested-By: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49046
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pmc.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 36fa59615b23..259a4a04d35f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -87,6 +87,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 3576d80969eb..7b00398a36a9 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -103,6 +103,8 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) +#define SLP_S0_RES 0x193c + #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) /* * The values for GPIO_CFG in Intel Document #572235 are incorrect. |