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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-04-19 18:03:46 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-07 17:20:26 +0000 |
| commit | 34508cd9ac51021721f3e9abfe2a69c8a9835a4b (patch) | |
| tree | 81dce468e15444049764c4e7fa22fad545419e22 | |
| parent | 553967256fa9941feae6c0044b09c5c8b87c398a (diff) | |
| download | coreboot-34508cd9ac51021721f3e9abfe2a69c8a9835a4b.tar.gz coreboot-34508cd9ac51021721f3e9abfe2a69c8a9835a4b.tar.bz2 coreboot-34508cd9ac51021721f3e9abfe2a69c8a9835a4b.zip | |
soc/intel/icelake: Add PM timer emulation support in ICL
CPU PM TIMER EMULATION logic will help UEFI payload to execute rather
wait for time tick in absence of TCO and ACPI PM timer after FSP-S.
BUG=N/A
TEST=Able to build and boot with tianocore payload.
Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/intel/icelake/cpu.c | 21 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/cpu.h | 3 |
2 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 05854502140a..f4ebacf96276 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -24,6 +24,7 @@ #include <fsp/api.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> #include <intelblocks/smm.h> #include <romstage_handoff.h> #include <soc/cpu.h> @@ -118,6 +119,23 @@ static void configure_dca_cap(void) } } +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable*/ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + static void set_energy_perf_bias(u8 policy) { msr_t msr; @@ -190,6 +208,9 @@ void soc_core_init(struct device *cpu) /* Configure Intel Speed Shift */ configure_isst(); + /* Enable PM timer emulation */ + enable_pm_timer_emulation(); + /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index 1e8d9e86c400..b5722da74230 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -35,6 +35,9 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ |