diff options
| author | Bo-Chen Chen <rex-bc.chen@mediatek.com> | 2022-11-23 17:24:25 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-05 14:25:58 +0000 |
| commit | 35693c5028754c80df200123a40cddf568cf0f16 (patch) | |
| tree | e233dcb8b97268b34283a2a2f85ec6ed7cc6631a | |
| parent | bb4c9ca2d68aa83d57c2d2839bbc81b6b2f23e1c (diff) | |
| download | coreboot-35693c5028754c80df200123a40cddf568cf0f16.tar.gz coreboot-35693c5028754c80df200123a40cddf568cf0f16.tar.bz2 coreboot-35693c5028754c80df200123a40cddf568cf0f16.zip | |
soc/mediatek/mt8188: Add support for MIPI panel
We need to add DSI and MIPI_TX settings to support MIPI panel.
BUG=b:244208960
TEST=emerge-geralt coreboot
Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70184
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/mediatek/mt8188/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/addressmap.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/dsi.h | 56 |
3 files changed, 59 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 59ec553affcb..7ac988b7505b 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += ../common/dfd.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c +ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index da959522313a..a5a3c00f6584 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -77,6 +77,7 @@ enum { I2C3_BASE = IO_PHYS + 0x01282000, SFLASH_REG_BASE = IO_PHYS + 0x0132C000, IOCFG_RM_BASE = IO_PHYS + 0x01C00000, + MIPITX_BASE = IO_PHYS + 0x01C80000, I2C1_BASE = IO_PHYS + 0x01E00000, I2C4_BASE = IO_PHYS + 0x01E01000, IOCFG_LT_BASE = IO_PHYS + 0x01E10000, @@ -95,6 +96,7 @@ enum { DISP_AAL0_BASE = IO_PHYS + 0x0C005000, DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000, DISP_DITHER0_BASE = IO_PHYS + 0x0C007000, + DSI0_BASE = IO_PHYS + 0x0C008000, DISP_OVL1_BASE = IO_PHYS + 0x0C00A000, DP_INTF0_BASE = IO_PHYS + 0x0C015000, DISP_MUTEX_BASE = IO_PHYS + 0x0C016000, diff --git a/src/soc/mediatek/mt8188/include/soc/dsi.h b/src/soc/mediatek/mt8188/include/soc/dsi.h new file mode 100644 index 000000000000..1a4eab43f6f9 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dsi.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8188_DSI_H +#define SOC_MEDIATEK_MT8188_DSI_H + +#include <soc/dsi_common.h> +#include <soc/dsi_register_v2.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif |