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| author | Felix Singer <felixsinger@posteo.net> | 2023-10-23 16:08:16 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-25 14:17:06 +0000 |
| commit | 3b01dd11cbe531b8ae0d34a2c994bd138601ed32 (patch) | |
| tree | 3b6348bf285422617c42f9d0a2c7051dea129878 | |
| parent | 21b5a9aff41136bacb3cce78ae027cd588c74295 (diff) | |
| download | coreboot-3b01dd11cbe531b8ae0d34a2c994bd138601ed32.tar.gz coreboot-3b01dd11cbe531b8ae0d34a2c994bd138601ed32.tar.bz2 coreboot-3b01dd11cbe531b8ae0d34a2c994bd138601ed32.zip | |
mb/facebook/monolith/devicetree: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.
While on it, remove superfluous comments related to modified settings.
Change-Id: I19af8c6b1167af793eb18b000fd93ec409385587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78597
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
| -rw-r--r-- | src/mainboard/facebook/monolith/devicetree.cb | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index cb3df2ee329a..7c4c53332625 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -181,19 +181,21 @@ chip soc/intel/skylake # Disable Aspm register "pcie_rp_aspm[8]" = "AspmDisabled" - # USB 2.0 Enable all ports - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 1 - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1 - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port - register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board - - # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1 + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */ + [1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */ + [2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */ + [3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */ + [4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */ + [6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */ + }" register "SsicPortEnable" = "0" |