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| author | Nico Huber <nico.h@gmx.de> | 2022-08-17 21:57:46 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-29 14:24:19 +0000 |
| commit | 49fc4e3e434afdcdc543b34cc60c9462ec08facf (patch) | |
| tree | 0cf9ac98537254e9a8bbf898192fd9f9a9955843 | |
| parent | 39564922a56feb18c85da8748bfb0f55b9fa1eeb (diff) | |
| download | coreboot-49fc4e3e434afdcdc543b34cc60c9462ec08facf.tar.gz coreboot-49fc4e3e434afdcdc543b34cc60c9462ec08facf.tar.bz2 coreboot-49fc4e3e434afdcdc543b34cc60c9462ec08facf.zip | |
pciexp: Move PCI path check one level up to pciexp_enable_ltr()
If we have a PCIe root port without `ops_pci` or without
`get_ltr_max_latencies`, the parent device wouldn't be PCI.
Hence, check for a PCI path early.
Change-Id: I358cb6756750bb10d0a23ab7133b917bfa25988b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/device/pciexp_device.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 449315bb295d..c8ac391c0687 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -211,8 +211,7 @@ static bool _pciexp_enable_ltr(struct device *parent, unsigned int parent_cap, return true; if (parent && - (parent->path.type != DEVICE_PATH_PCI || - !_pciexp_ltr_supported(parent, parent_cap) || + (!_pciexp_ltr_supported(parent, parent_cap) || !_pciexp_ltr_enabled(parent, parent_cap))) return false; @@ -235,6 +234,8 @@ static void pciexp_enable_ltr(struct device *dev) unsigned int parent_cap = 0; if (!dev->ops->ops_pci || !dev->ops->ops_pci->get_ltr_max_latencies) { parent = dev->bus->dev; + if (parent->path.type != DEVICE_PATH_PCI) + return; parent_cap = pci_find_capability(parent, PCI_CAP_ID_PCIE); if (!parent_cap) return; |