nb/x4x/dq_dqs.c: Use 'enum cb_err'

Change-Id: I94dd6b1bb81bbc38ac5f89469b3ed7c83ca2a498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

2 files changed, 12 insertions, 12 deletions

diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 870e660810c4..4355717579aa 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -74,7 +74,7 @@ static void set_db(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
 
 static const u8 max_tap[3] = {12, 10, 13};
 
-static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
+static enum cb_err increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
 {
 	u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
 
@@ -99,7 +99,7 @@ static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_
 	return CB_SUCCESS;
 }
 
-static int decrement_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
+static enum cb_err decrement_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
 {
 	u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
 
@@ -195,12 +195,12 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel)
  * This is probably done because lanes cannot be trained independent from
  * each other.
  */
-static int find_dq_limit(const struct sysinfo *s, const u8 channel,
+static enum cb_err find_dq_limit(const struct sysinfo *s, const u8 channel,
 			struct dll_setting dq_setting[TOTAL_BYTELANES],
 			u8 dq_lim[TOTAL_BYTELANES],
 			const enum training_modes expected_result)
 {
-	int status = CB_SUCCESS;
+	enum cb_err status = CB_SUCCESS;
 	int lane;
 	u8 test_result;
 	u8 pass_count[TOTAL_BYTELANES];
@@ -250,7 +250,7 @@ static int find_dq_limit(const struct sysinfo *s, const u8 channel,
  * - note: bytelanes cannot be trained independently, so the delays need to be
  *   adjusted and tested for all of them at the same time
  */
-int do_write_training(struct sysinfo *s)
+enum cb_err do_write_training(struct sysinfo *s)
 {
 	int i;
 	u8 channel, lane;
@@ -328,7 +328,7 @@ static const u32 read_training_schedule[RT_PATTERN_SIZE] = {
 	0xdfdfdfdf, 0xbebebebe, 0x7f7f7f7f, 0xfefefefe
 };
 
-static int rt_increment_dqs(struct rt_dqs_setting *setting)
+static enum cb_err rt_increment_dqs(struct rt_dqs_setting *setting)
 {
 	if (setting->pi < 7) {
 		setting->pi++;
@@ -364,14 +364,14 @@ static u8 test_dqs_aligned(const struct sysinfo *s, const u8 channel)
 	return bytelane_error;
 }
 
-static int rt_find_dqs_limit(struct sysinfo *s, u8 channel,
+static enum cb_err rt_find_dqs_limit(struct sysinfo *s, u8 channel,
 			struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES],
 			u8 dqs_lim[TOTAL_BYTELANES],
 			const enum training_modes expected_result)
 {
 	int lane;
 	u8 test_result;
-	int status = CB_SUCCESS;
+	enum cb_err status = CB_SUCCESS;
 
 	FOR_EACH_BYTELANE(lane)
 		rt_set_dqs(channel, lane, 0, &dqs_setting[lane]);
@@ -418,7 +418,7 @@ static int rt_find_dqs_limit(struct sysinfo *s, u8 channel,
  *   seems to be required, most likely because the signals can't really be generated
  *   separately.
  */
-int do_read_training(struct sysinfo *s)
+enum cb_err do_read_training(struct sysinfo *s)
 {
 	int loop, channel, i, lane, rank;
 	u32 address, content;
diff --git a/src/northbridge/intel/x4x/raminit.h b/src/northbridge/intel/x4x/raminit.h
index ca58b1f5c0bd..c2011a69bab6 100644
--- a/src/northbridge/intel/x4x/raminit.h
+++ b/src/northbridge/intel/x4x/raminit.h
@@ -3,7 +3,7 @@
 #ifndef __X4X_RAMINIT_H__
 #define __X4X_RAMINIT_H__
 
-#include <stdint.h>
+#include <types.h>
 
 #define NOP_CMD		0x2
 #define PRECHARGE_CMD	0x4
@@ -218,8 +218,8 @@ u32 test_address(int channel, int rank);
 void dqsset(u8 ch, u8 lane, const struct dll_setting *setting);
 void dqset(u8 ch, u8 lane, const struct dll_setting *setting);
 void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting);
-int do_write_training(struct sysinfo *s);
-int do_read_training(struct sysinfo *s);
+enum cb_err do_write_training(struct sysinfo *s);
+enum cb_err do_read_training(struct sysinfo *s);
 void search_write_leveling(struct sysinfo *s);
 void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val);