diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-06-02 20:10:36 +0200 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-10 17:01:25 +0000 |
commit | 4def30d550a58ff7fa599c41cddb7ffca7e5077e (patch) | |
tree | 8b439ee27911f3001000c15e0874ed574100a37b | |
parent | 3fe1ad1f26314e9926037e7b0025b65582a34a75 (diff) | |
download | coreboot-4def30d550a58ff7fa599c41cddb7ffca7e5077e.tar.gz coreboot-4def30d550a58ff7fa599c41cddb7ffca7e5077e.tar.bz2 coreboot-4def30d550a58ff7fa599c41cddb7ffca7e5077e.zip |
sb/intel/bd82x6x: Make me_common.c a compilation unit
We need to make most things non-static so that the code builds. Also, we
need to update ibexpeak as well, because it borrows files from bd82x6x.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42019
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 3 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/me.c | 3 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/me.h | 27 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 3 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/me_common.c | 37 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/Makefile.inc | 3 |
6 files changed, 51 insertions, 25 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 3b10201930bd..687fc97d4ce5 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -16,6 +16,7 @@ ramstage-y += usb_ehci.c ramstage-y += usb_xhci.c ramstage-y += me.c ramstage-y += me_8.x.c +ramstage-y += me_common.c ramstage-y += smbus.c ramstage-y += ../common/pciehp.c @@ -25,7 +26,7 @@ ramstage-y += me_status.c ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c +smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c romstage-y += me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 3a1ba55cec66..c51cca61d58c 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -27,9 +27,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index c26078ff6ca7..014fc1d9eac0 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -220,6 +220,33 @@ typedef enum { ME_FIRMWARE_UPDATE_BIOS_PATH, } me_bios_path; +/* Defined in me_common.c for both ramstage and smm */ +const char *const me_get_bios_path_string(int path); + +void mei_read_dword_ptr(void *ptr, int offset); +void mei_write_dword_ptr(void *ptr, int offset); + +#ifndef __SIMPLE_DEVICE__ +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset); +#endif + +void read_host_csr(struct mei_csr *csr); +void write_host_csr(struct mei_csr *csr); + +void read_me_csr(struct mei_csr *csr); + +void write_cb(u32 dword); +u32 read_cb(void); + +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes); + +void update_mei_base_address(void); +bool is_mei_base_address_valid(void); +int intel_mei_setup(struct device *dev); +int intel_me_extend_valid(struct device *dev); +void intel_me_hide(struct device *dev); + /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 4d232ede9cb3..d47c1da6b8aa 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -27,9 +27,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index cdfd83224c46..ae157d36c30b 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -16,7 +16,7 @@ #include "pch.h" /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] __unused = { +static const char *const me_bios_path_values[] = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -25,7 +25,7 @@ static const char *me_bios_path_values[] __unused = { [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static inline const char *const me_get_bios_path_string(int path) +const char *const me_get_bios_path_string(int path) { return me_bios_path_values[path]; } @@ -70,14 +70,14 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) * ME/MEI access helpers using memcpy to avoid aliasing. */ -static inline void mei_read_dword_ptr(void *ptr, int offset) +void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset / sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } -static inline void mei_write_dword_ptr(void *ptr, int offset) +void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); @@ -86,7 +86,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SIMPLE_DEVICE__ -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -94,28 +94,28 @@ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) } #endif -static inline void read_host_csr(struct mei_csr *csr) +void read_host_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_H_CSR); } -static inline void write_host_csr(struct mei_csr *csr) +void write_host_csr(struct mei_csr *csr) { mei_write_dword_ptr(csr, MEI_H_CSR); } -static inline void read_me_csr(struct mei_csr *csr) +void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); } -static inline void write_cb(u32 dword) +void write_cb(u32 dword) { write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } -static inline u32 read_cb(void) +u32 read_cb(void) { u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); @@ -175,6 +175,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, void * /* Pad non-dword aligned request message length */ if (mei->length & 3) ndata++; + if (!ndata) { printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); return -1; @@ -250,6 +251,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) break; udelay(ME_DELAY); } + if (!n) { printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n", expected, me.buffer_write_ptr - me.buffer_read_ptr); @@ -267,6 +269,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) ndata = mei_rsp.length >> 2; if (mei_rsp.length & 3) ndata++; + if (ndata != (expected - 1)) { printk(BIOS_ERR, "ME: response is missing data %d != %d\n", ndata, (expected - 1)); @@ -307,8 +310,8 @@ static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) return mei_wait_for_me_ready(); } -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -319,13 +322,13 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, #ifdef __SIMPLE_DEVICE__ -static inline void update_mei_base_address(void) +void update_mei_base_address(void) { uint32_t reg32 = pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; mei_base_address = (u32 *)(uintptr_t)reg32; } -static inline bool is_mei_base_address_valid(void) +bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } @@ -333,7 +336,7 @@ static inline bool is_mei_base_address_valid(void) #else /* Prepare ME for MEI messages */ -static int intel_mei_setup(struct device *dev) +int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -364,7 +367,7 @@ static int intel_mei_setup(struct device *dev) #endif /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(struct device *dev) +int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -411,7 +414,7 @@ static int intel_me_extend_valid(struct device *dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(struct device *dev) +void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index a146187918e8..277f686ba912 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -14,6 +14,7 @@ ramstage-y += sata.c ramstage-y += usb_ehci.c ramstage-y += me.c ramstage-y += ../bd82x6x/me_8.x.c +ramstage-y += ../bd82x6x/me_common.c ramstage-y += smbus.c ramstage-y += thermal.c ramstage-y += ../common/pciehp.c @@ -25,7 +26,7 @@ ramstage-y += ../bd82x6x/me_status.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c ramstage-y += madt.c -smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c +smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/me_common.c romstage-y += early_pch.c romstage-y +=../bd82x6x/early_me.c |