mb/hp/z220_series: Improve the port for z220_sff_workstation

- Move configs for PCIe ports not present on z220_sff_workstation
  from the devicetree.cb of base board to the overridetree.cb of
  z220_cmt_workstation.

- Add a note for ME/AMT Flash Override jumper, for it is hard to
  flash from OEM firmware either internally or externally without
  closing this jumper.

- Add a side note for similar HP Compaq Elite 8300 SFF.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 18 insertions, 4 deletions

diff --git a/Documentation/mainboard/hp/z220_sff.md b/Documentation/mainboard/hp/z220_sff.md
index 0dfa65393705..11676208ac74 100644
--- a/Documentation/mainboard/hp/z220_sff.md
+++ b/Documentation/mainboard/hp/z220_sff.md
@@ -44,8 +44,17 @@ The SPI flash can be accessed using [flashrom].
 External programming with an SPI adapter and [flashrom] does work, but it powers the
 whole southbridge complex. You need to supply enough current through the programming adapter.
 
-If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
-as otherwise there's not enough space near the flash.
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, as
+otherwise there's not enough space near the flash.
+
+In both case, if ME has not been completely disabled, ME/AMT Flash Override jumper had better
+be temporary closed for flashing to disable the locking of regions, and prevent ME to run and
+interfere.
+
+## Side note
+The mainboard of [HP Compaq Elite 8300 SFF] is very similar to the one of Z220 SFF, except
+that Compaq Elite 8300 uses Q77 instead of C216 for its PCH, and their boot firmwares are
+even interchangeable, so should do coreboot images built for them.
 
 ## Technology
 
@@ -66,5 +75,6 @@ as otherwise there's not enough space near the flash.
 ```
 
 [HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
+[HP Compaq Elite 8300 SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom
diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb
index 4611bec14089..ea8fad93205a 100644
--- a/src/mainboard/hp/z220_series/devicetree.cb
+++ b/src/mainboard/hp/z220_series/devicetree.cb
@@ -22,6 +22,7 @@ chip northbridge/intel/sandybridge
 		device pci 00.0 on  end	# Host bridge Host bridge
 		device pci 01.0 on  end	# PCIe Bridge for discrete graphics
 		device pci 02.0 on  end	# Internal graphics VGA controller
+		device pci 06.0 off end	# Extra x4 port on north bridge
 
 		chip southbridge/intel/bd82x6x # Intel Series 7 PCH
 			register "docking_supported" = "0"
@@ -47,8 +48,8 @@ chip northbridge/intel/sandybridge
 			device pci 1c.3 off end	# PCIe Port #4
 			device pci 1c.4 on  end	# PCIe Port #5
 			device pci 1c.5 off end	# PCIe Port #6
-			device pci 1c.6 on  end	# PCIe Port #7
-			device pci 1c.7 on  end	# PCIe Port #8
+			device pci 1c.6 off end	# PCIe Port #7
+			device pci 1c.7 off end	# PCIe Port #8
 			device pci 1d.0 on  end	# USB2 EHCI #1
 			device pci 1e.0 on  end	# PCI bridge
 			device pci 1f.0 on	# LPC bridge PCI-LPC bridge
diff --git a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb
index 2e46d2a0b691..55bdaac23a2a 100644
--- a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb
+++ b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb
@@ -3,6 +3,7 @@
 chip northbridge/intel/sandybridge
 	device domain 0 on
 		subsystemid 0x103c 0x1791 inherit
+		device pci 06.0 on  end	# Extra x4 port on north bridge
 		chip southbridge/intel/bd82x6x
 			register "sata_port_map" = "0x3f"
 
@@ -10,6 +11,8 @@ chip northbridge/intel/sandybridge
 			device pci 1c.2 on  end	# PCIe Port #3
 			device pci 1c.3 on  end	# PCIe Port #4
 			device pci 1c.5 on  end	# PCIe Port #6
+			device pci 1c.6 on  end	# PCIe Port #7
+			device pci 1c.7 on  end	# PCIe Port #8
 		end
 	end
 end