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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2023-04-26 19:57:12 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-04-27 14:40:48 +0000 |
| commit | 544e2aa21566ddc75673ccb84633e6bb381ecb24 (patch) | |
| tree | 9262a34aa221ec44b6ae9c52a376539497df276f | |
| parent | f9270265360930a46387d617c18e55e67833edfb (diff) | |
| download | coreboot-544e2aa21566ddc75673ccb84633e6bb381ecb24.tar.gz coreboot-544e2aa21566ddc75673ccb84633e6bb381ecb24.tar.bz2 coreboot-544e2aa21566ddc75673ccb84633e6bb381ecb24.zip | |
mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
Set edp_panel_t9_ms to 8ms which means it will delay 8ms
between backlight off and vary backlight off.
BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was passed to system integrated table;
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/skyrim/variants/winterhold/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 2e32b289199f..d8603b7c38ef 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -114,6 +114,7 @@ chip soc/amd/mendocino # The unit is set to one per ms register "edp_panel_t8_ms" = "112" + register "edp_panel_t9_ms" = "8" device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. |