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| author | Felix Singer <felixsinger@posteo.net> | 2021-12-05 07:36:13 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-12-12 16:06:31 +0000 |
| commit | 5588f34a35209f34d9061e6a83856289450d8131 (patch) | |
| tree | e789f9bbedd7e5bf7e51c348054913f70d746a00 | |
| parent | 610b016caf3170fc2bd92603bd75c1e69d4cbeb6 (diff) | |
| download | coreboot-5588f34a35209f34d9061e6a83856289450d8131.tar.gz coreboot-5588f34a35209f34d9061e6a83856289450d8131.tar.bz2 coreboot-5588f34a35209f34d9061e6a83856289450d8131.zip | |
mainboard: Drop `SataMode` setting from Tiger Lake devicetrees
All Tiger Lake mainboards use the default value for the setting
`SataMode`. Thus, drop it from their devicetree.
Change-Id: I291048250bc82552fde7c71a1dcda4894a61d465
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59890
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index aeab2d4bf269..067222440c84 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/tigerlake # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SataMode" = "0" register "SataSalpSupport" = "1" # TODO: the lengths are all MID for right now. diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1958e997916a..a93a38a8306d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -146,7 +146,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" # Enable SATA - register "SataMode" = "0" register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" |