soc/intel/cannonlake: Make use of Intel SPI common block

TEST=Build and boot RVP

Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

3 files changed, 2 insertions, 56 deletions

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 92aad2817f63..36ea922ba931 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -65,6 +65,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_SMBUS
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+	select SOC_INTEL_COMMON_BLOCK_SPI
 	select SOC_INTEL_COMMON_BLOCK_TIMER
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index de137f629a26..076e76b95288 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -54,13 +54,11 @@ ramstage-y += sd.c
 smm-y += gpio.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
 smm-$(CONFIG_UART_DEBUG) += uart.c
 smm-$(CONFIG_UART_DEBUG) += uart_pch.c
 
 postcar-y += memmap.c
 postcar-y += pmutil.c
-postcar-y += spi.c
 postcar-$(CONFIG_UART_DEBUG) += uart.c
 
 verstage-y += gspi.c
diff --git a/src/soc/intel/cannonlake/spi.c b/src/soc/intel/cannonlake/spi.c
index a86f760ec8b4..a601624a5ebb 100644
--- a/src/soc/intel/cannonlake/spi.c
+++ b/src/soc/intel/cannonlake/spi.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright 2017 Google Inc.
+ * Copyright 2017 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,18 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/spi.h>
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/gspi.h>
 #include <intelblocks/spi.h>
-#include <soc/ramstage.h>
 #include <soc/pci_devs.h>
-#include <spi-generic.h>
 
 int spi_soc_devfn_to_bus(unsigned int devfn)
 {
@@ -56,47 +47,3 @@ int spi_soc_bus_to_devfn(unsigned int bus)
 	}
 	return -1;
 }
-
-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
-	{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
-#if !ENV_SMM
-	{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
-	  .bus_end =  1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
-#endif
-};
-
-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
-
-#if ENV_RAMSTAGE
-
-static int spi_dev_to_bus(struct device *dev)
-{
-	return spi_soc_devfn_to_bus(dev->path.pci.devfn);
-}
-
-static struct spi_bus_operations spi_bus_ops = {
-	.dev_to_bus			= &spi_dev_to_bus,
-};
-
-static struct device_operations spi_dev_ops = {
-	.read_resources			= &pci_dev_read_resources,
-	.set_resources			= &pci_dev_set_resources,
-	.enable_resources		= &pci_dev_enable_resources,
-	.scan_bus			= &scan_generic_bus,
-	.ops_spi_bus			= &spi_bus_ops,
-};
-
-static const unsigned short pci_device_ids[] = {
-	PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI,
-	PCI_DEVICE_ID_INTEL_CNL_SPI0,
-	PCI_DEVICE_ID_INTEL_CNL_SPI1,
-	PCI_DEVICE_ID_INTEL_CNL_SPI2,
-	0
-};
-
-static const struct pci_driver pch_spi __pci_driver = {
-	.ops				= &spi_dev_ops,
-	.vendor				= PCI_VENDOR_ID_INTEL,
-	.devices			= pci_device_ids,
-};
-#endif