summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2024-01-18 21:10:59 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-01-20 01:27:04 +0000
commit5b94f9a663b08ff73466c0ee97594367729ae919 (patch)
tree277c8011c404ced11ae969098536f780f747d4d5
parent931840fbcbe9bbe9cd98a4fbc26bfa45433a13c2 (diff)
downloadcoreboot-5b94f9a663b08ff73466c0ee97594367729ae919.tar.gz
coreboot-5b94f9a663b08ff73466c0ee97594367729ae919.tar.bz2
coreboot-5b94f9a663b08ff73466c0ee97594367729ae919.zip
soc/amd/*/romstage: factor out FSP-M call
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code and a preparation to make the romstage of all non-CAR AMD SoCs common. Without isolating the call into the FSP-M code, building the common romstage would fail for genoa_poc due to fsp/api.h not being in the include path. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/80002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-rw-r--r--src/soc/amd/cezanne/romstage.c5
-rw-r--r--src/soc/amd/common/block/include/amdblocks/fsp.h8
-rw-r--r--src/soc/amd/common/fsp/Makefile.inc1
-rw-r--r--src/soc/amd/common/fsp/fsp_romstage.c10
-rw-r--r--src/soc/amd/glinda/romstage.c5
-rw-r--r--src/soc/amd/mendocino/romstage.c5
-rw-r--r--src/soc/amd/phoenix/romstage.c5
-rw-r--r--src/soc/amd/picasso/romstage.c5
8 files changed, 29 insertions, 15 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 63a6b07dc632..6b84728ad1cb 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -18,7 +17,7 @@ void __noreturn romstage_main(void)
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/common/block/include/amdblocks/fsp.h b/src/soc/amd/common/block/include/amdblocks/fsp.h
new file mode 100644
index 000000000000..a7b664f498bc
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/fsp.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_FSP_H
+#define AMD_BLOCK_FSP_H
+
+void amd_fsp_early_init(void);
+
+#endif /* AMD_BLOCK_FSP_H */
diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc
index 14f1f8510b77..2517f0c6fe55 100644
--- a/src/soc/amd/common/fsp/Makefile.inc
+++ b/src/soc/amd/common/fsp/Makefile.inc
@@ -2,6 +2,7 @@
ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
romstage-y += fsp_memmap.c
romstage-y += fsp_reset.c
+romstage-y += fsp_romstage.c
romstage-y += fsp_validate.c
ramstage-y += fsp_graphics.c
ramstage-y += fsp_memmap.c
diff --git a/src/soc/amd/common/fsp/fsp_romstage.c b/src/soc/amd/common/fsp/fsp_romstage.c
new file mode 100644
index 000000000000..26778f19229d
--- /dev/null
+++ b/src/soc/amd/common/fsp/fsp_romstage.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <amdblocks/fsp.h>
+#include <fsp/api.h>
+
+void amd_fsp_early_init(void)
+{
+ fsp_memory_init(acpi_is_wakeup_s3());
+}
diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c
index 63a6b07dc632..6b84728ad1cb 100644
--- a/src/soc/amd/glinda/romstage.c
+++ b/src/soc/amd/glinda/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -18,7 +17,7 @@ void __noreturn romstage_main(void)
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c
index 83a8bf97504b..f1ee595c84f6 100644
--- a/src/soc/amd/mendocino/romstage.c
+++ b/src/soc/amd/mendocino/romstage.c
@@ -1,14 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <amdblocks/stb.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -22,7 +21,7 @@ void __noreturn romstage_main(void)
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/phoenix/romstage.c b/src/soc/amd/phoenix/romstage.c
index 63a6b07dc632..6b84728ad1cb 100644
--- a/src/soc/amd/phoenix/romstage.c
+++ b/src/soc/amd/phoenix/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -18,7 +17,7 @@ void __noreturn romstage_main(void)
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index c43b249487be..5159061b9a38 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
#include <types.h>
@@ -19,7 +18,7 @@ void __noreturn romstage_main(void)
/* Snapshot chipset state prior to any FSP call. */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
memmap_stash_early_dram_usage();