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| author | David Hendricks <dhendrix@chromium.org> | 2014-11-03 17:42:09 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-04-10 16:47:44 +0200 |
| commit | 627b3bd2b09e4daf40001f2a7833df3ef2a257b2 (patch) | |
| tree | 1ab02371b56f7cdf7477cfcc6c61ae602fff5531 | |
| parent | ceaabc94efec339f75732dd7bf72c51f8dc52941 (diff) | |
| download | coreboot-627b3bd2b09e4daf40001f2a7833df3ef2a257b2.tar.gz coreboot-627b3bd2b09e4daf40001f2a7833df3ef2a257b2.tar.bz2 coreboot-627b3bd2b09e4daf40001f2a7833df3ef2a257b2.zip | |
cbtables: Add RAM config information
This adds the RAM config code to the coreboot tables. The purpose is
to expose this information to software running at higher levels, e.g.
to print the RAM config coreboot is using as part of factory tests.
The prototype for ram_code() is in boardid.h since they are closely
related and will likely have common code.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=tested w/ follow-up CLs on pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400
Original-Reviewed-on: https://chromium-review.googlesource.com/227248
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 77dd5fb9347b53bb8a64ad22341257fb3be0c106)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ibe7044cafe0a61214ac2d7fea5f7255b2c11829b
Reviewed-on: http://review.coreboot.org/9438
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/Kconfig | 7 | ||||
| -rw-r--r-- | src/include/boardid.h | 1 | ||||
| -rw-r--r-- | src/include/boot/coreboot_tables.h | 7 | ||||
| -rw-r--r-- | src/lib/coreboot_table.c | 16 |
4 files changed, 31 insertions, 0 deletions
diff --git a/src/Kconfig b/src/Kconfig index 7c325c292b12..569e404224fe 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -253,6 +253,13 @@ config UPDATE_IMAGE is a suitable file for further processing. The bootblock will not be modified. +config RAM_CODE_SUPPORT + bool "Discover RAM configuration code and store it in coreboot table" + default n + help + If enabled, coreboot discovers RAM configuration (value obtained by + reading board straps) and stores it in coreboot table. + endmenu source "src/mainboard/Kconfig" diff --git a/src/include/boardid.h b/src/include/boardid.h index d1c6ad975690..41c21d6e31a3 100644 --- a/src/include/boardid.h +++ b/src/include/boardid.h @@ -23,5 +23,6 @@ #include <stdint.h> uint8_t board_id(void); +uint32_t ram_code(void); #endif /* __INCLUDE_BOARDID_H__ */ diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index db55adaa366e..56394733cefe 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -276,6 +276,13 @@ struct lb_macs { struct mac_address mac_addrs[0]; }; +#define LB_TAG_RAM_CODE 0x0028 +struct lb_ram_code { + uint32_t tag; + uint32_t size; + uint32_t ram_code; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 365283fffe07..332bed172ac5 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -227,6 +227,19 @@ static void lb_board_id(struct lb_header *header) #endif } +static void lb_ram_code(struct lb_header *header) +{ +#if IS_ENABLED(CONFIG_RAM_CODE_SUPPORT) + struct lb_ram_code *code; + + code = (struct lb_ram_code *)lb_new_record(header); + + code->tag = LB_TAG_RAM_CODE; + code->size = sizeof(*code); + code->ram_code = ram_code(); +#endif +} + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -452,6 +465,9 @@ unsigned long write_coreboot_table( /* Add board ID if available */ lb_board_id(head); + /* Add RAM config if available */ + lb_ram_code(head); + add_cbmem_pointers(head); /* Add board-specific table entries, if any. */ |