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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2021-09-11 08:17:39 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2021-09-13 09:49:51 +0000 |
| commit | 63df43d7154b38d1baebf5a88645b4175e029efa (patch) | |
| tree | 3e14b3bac8974ec051e6d6e3e3004f4c33be1d51 | |
| parent | 48ae111ca80e5d35e2fa25fe39cf01bb2fc6e087 (diff) | |
| download | coreboot-63df43d7154b38d1baebf5a88645b4175e029efa.tar.gz coreboot-63df43d7154b38d1baebf5a88645b4175e029efa.tar.bz2 coreboot-63df43d7154b38d1baebf5a88645b4175e029efa.zip | |
mb/prodrive/hermes: Hook up P2SB and PMC in devicetree
Fixes commit bd5b4aa683a634a73a6a63d1f197e2bb74b6a80e
"soc/intel/cannonlake: Switch PMC to use device callbacks" as it
requires the PCI device 1f.2 to be present in the devicetree.
It was missing for this mainboard and caused a boot failure.
Change-Id: Iaf508b2d955578efa2a266af50c568f5c0a47aaf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/mainboard/prodrive/hermes/devicetree.cb | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index b7e89dc537fa..cafc81e6ba35 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -38,9 +38,11 @@ chip soc/intel/cannonlake end # AST2500, but not enabled to decode LPC cycles end - device pci 1f.3 on end - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI end end |