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| author | Wisley Chen <wisley.chen@quantatw.com> | 2016-11-15 03:51:13 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-17 18:48:49 +0100 |
| commit | 676b4878971b2fd782fbf97095d7cf0867ba00fe (patch) | |
| tree | 2f614c118889a20e2f8159d78d785d7f07e7e465 | |
| parent | 9f2a411042c11d89d8e0a9c5459f5a250a505486 (diff) | |
| download | coreboot-676b4878971b2fd782fbf97095d7cf0867ba00fe.tar.gz coreboot-676b4878971b2fd782fbf97095d7cf0867ba00fe.tar.bz2 coreboot-676b4878971b2fd782fbf97095d7cf0867ba00fe.zip | |
google/snappy: Update DPTF settings
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
CPU passive point:100, critical point:105
TSR1 passive point:48, critial point:65
TSR2 passive point:85, critial point:100
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 3W, and max to 6W
Set PL2 min and max to 8W
3. Change thermal relationship table (TRT) setting.
The TRT of TCHG is TSR1, but real sensor is TSR2.
BRANCH=master
BUG=none
TEST= Compiled, verified by thermal team.
Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17426
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl index 43e2e930450c..f0e605be5bc1 100644 --- a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 95 -#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_PASSIVE 100 +#define DPTF_CPU_CRITICAL 105 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 80 #define DPTF_CPU_ACTIVE_AC2 70 @@ -29,12 +29,12 @@ #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Ambient" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_PASSIVE 48 +#define DPTF_TSR1_CRITICAL 65 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_PASSIVE 85 #define DPTF_TSR2_CRITICAL 100 #define DPTF_ENABLE_CHARGER @@ -57,11 +57,11 @@ Name (DTRT, Package () { #ifdef DPTF_ENABLE_CHARGER /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 }, #endif /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 2 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, @@ -72,15 +72,15 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 1600, /* PowerLimitMinimum */ - 12000, /* PowerLimitMaximum */ + 3000, /* PowerLimitMinimum */ + 6000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ + 300 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMinimum */ 8000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ |